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rev.1.04 aug 23, 2007 page 1 of 146 rej03b0188-0104 description the 4559 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with two 8-bit timers (each timer ha s one or two reload registers), a 16-bit timer for clock count, interrupts, and oscillation circuit switch function. the various microcomputers in the 4559 group include variations of type as shown in the table below. features ? minimum instruction execution time..............................0.5 s (at 6 mhz oscillati on frequency, in high-speed through-mode) ? supply voltage ........ ........... ........... ........... ............ ..1.8 to 5.5 v (it depends on operation sour ce clock, oscillation frequency and operation mode) ?timers timer 1..............................................................8-bit timer with a reload register and carrier wa ve output auto-control function timer 2.....................................................................8-bit timer with two reload registers a nd carrier wave generation circuit timer 3........................ 16-bit timer (fixed dividing frequency) ? interrupt ..................................................................... 4 sources ? key-on wakeup function pins .............................................. 17 ? i/o port ................................................................................. 22 ? output port ............................................................................. 3 ? lcd control circuit segment output ..................................................................... 32 common output ...................................................................... 4 ? voltage drop detection circuit reset occurrence..................................typ. 1.7 v (ta = 25 c) reset release ........................................typ. 1.8 v (ta = 25 c) skip occurrence ...................................typ. 2.0 v (ta = 25 c) ? power-on reset circuit ? watchdog timer ? clock generating circuit built-in clock (on-chip oscillator) main clock (ceramic resonator/rc oscillation) sub-clock (quart z-crystal oscillation) ? led drive directly enabled (port d) application remote control transmitter note 1: shipped in blank table 1 support product part number rom size ( 10 bits) ram size ( 4 bits) package rom type m34559g6fp (note 1) 6144 words 288 words plqp0052ja-a qzrom m34559g6-xxxfp 6144 words 288 words plqp0052ja-a qzrom 4559 group single-chip 4-bit cmos microcomputer rej03b0188-0104 rev.1.04 aug 23, 2007
rev.1.04 aug 23, 2007 page 2 of 146 rej03b0188-0104 4559 group pin configuration fig 1. pin configuration (plqp0052ja-a type) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 d 2 d 3 d 4 d 5 /int cnvss x cin /d 6 x cout /d 7 reset x out vss x in v dd c/cntr p1 0 /seg 20 p0 3 /seg 19 p0 2 /seg 18 p0 1 /seg 17 p0 0 /seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 /v lc1 seg 1 /v lc2 seg 0 /v lc3 com 3 com 2 com 1 com 0 vdce p1 1 /seg 21 p1 2 /seg 22 p1 3 /seg 23 p2 0 /seg 24 p2 1 /seg 25 p2 2 /seg 26 p2 3 /seg 27 p3 0 /seg 28 p3 1 /seg 29 p3 2 /seg 30 p3 3 /seg 31 d 0 d 1 m34559g6fp m34559g6-xxxfp outline plqp0052ja-a (52p6a-a) pin configuration (top view)
rev.1.04 aug 23, 2007 page 3 of 146 rej03b0188-0104 4559 group functional block diagram fig 2. functional block diagram (plqp0052ja-a type) ram 288 words 4 bits lcd display ram including 32 words 4 bits rom 6144 words 10 bits memory i/o port internal peripheral functions timer timer 1 (8 bits) timer 2 (8 bits) timer 3 (16 bits) 4500 series cpu core register a (4 bits) register b (4 bits) register d (3 bits) register e (8 bits) stack register sk (8 levels) interrupt stack register sdp (1 level) alu (4 bits) watchdog timer (16 bits) port p0 4 port p1 4 port p2 4 port d 6 system clock generating circuit x in -x out (ceramic/rc) x cin -x cout (quartz-crystal) on-chip oscillator voltage drop detection circuit port p3 4 port c 1 2 power-on reset circuit lcd drive control circuit (max.32 segments 4 common) common output 4 segment output 32
rev.1.04 aug 23, 2007 page 4 of 146 rej03b0188-0104 4559 group performance overview table 2 performance overview parameter function number of basic instructions 135 minimum instruction execution time 0.5 s (oscillation frequency 6 mhz: high-speed through mode) memory sizes rom 6144 words 10 bits ram 288 words 4 bits (including lcd display ram 32 words 4 bits) i/o port d 0 ? d 5 i/o (input is examined by skip decision.) six independent i/o ports. the output structure can be switched by software. port d 5 is also used as int pin. d 6 , d 7 output two independent output ports. ports d 6 and d 7 are also used as x cin and x cout , respectively. p0 0 ? p0 3 i/o 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. ports p0 0 ? p0 3 are also used as seg 16 ? seg 19 , respectively. p1 0 ? p1 3 i/o 4-bit i/o port; a pull-up function, a key- on wakeup function and output structure can be switched by software. ports p1 0 ? p1 3 are also used as seg 20 ? seg 23 , respectively. p2 0 ? p2 3 i/o 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. ports p2 0 ? p2 3 are also used as seg 24 ? seg 27 , respectively. p3 0 ? p3 3 i/o 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. ports p3 0 ? p3 3 are also used as seg 28 ? seg 31 , respectively. c output 1-bit output; port c is also used as cntr pin. timer timer 1 8-bit timer with a reload register and carrier wave output auto-control function, and has an event counter. timer 2 8-bit timer with two reload regist ers and carrier wave generation function. timer 3 16-bit timer, fixed dividi ng frequency (timer for clock count) timer lc 4-bit programmable timer with a reload register (for lcd clock generating) watchdog timer 16-bit timer, fixed di viding frequency (timer for monitor) lcd control circuit selective bias value 1/2, 1/3 bias selective duty value 2, 3, 4 duty common output 4 segment output 32 internal resistor for power supply 2r 3, 2r 2, r 3, r 2 (r = 100 k ? , (ta = 25 c, typical value)) voltage drop detection circuit reset occurrence typ. 1.7 v (ta=25 c) reset release typ. 1.8 v (ta=25 c) skip occurrence typ. 2.0 v (ta=25 c) power-on reset circuit built-in interrupt source 4 sources (one for external, three for timers) nesting 1 level subroutine nesting 8 levels device structure cmos silicon gate package 52-pin plastic mo lded lqfp (plqp0052ja-a) operating temperature range -20 to 85 c power source voltage 1.8 to 5.5 v (it depends on op eration source cl ock, oscillation frequency and operation mode) power dissipation (typ. value) at active mode 0.3 ma (ta = 25 c, v dd = 3 v, f(x in ) = 4 mhz, f(x cin ) = stop, f(ring) = stop, f(stck) = f(x in )/8 at clock operating mode 5 a (ta = 25 c, v dd = 3 v, f(x cin ) = 32 khz) at ram back-up 0.1 a (ta = 25 c, v dd = 5 v, output transistor is cut-off state)
rev.1.04 aug 23, 2007 page 5 of 146 rej03b0188-0104 4559 group pin description table 3 pin description pin name input/output function v dd power source ? connected to a plus power supply. v ss power source ? connected to a 0 v power supply. cnv ss cnv ss ? this pin is shared with the v pp pin which is the power source input pin for programming the built-in qzrom. connect to v ss through a resistor about 5 k ? . vdce voltage drop detection circuit enable input this pin is used to operate/st op the voltage drop detection circuit. when ?h? level is input to this pin, the circuit starts operating. when ?l? level is input to this pin, the circuit stops operating. x in main clock input input i/o pins of the main clock generating circuit. when using a ceramic resonator, connect it between pins x in and x out . a feedback resistor is built-in between them. when using the rc oscillation, connect a resistor and a capacitor to x in , and leave x out pin open. x out main clock output output x cin sub clock input input i/o pins of the sub-clock generating circuit. connect a 32.768 khz quartz-crystal oscillator between pins x cin and x cout . a feedback resistor is built-in between them. x cin and x cout pins are also used as ports d 6 and d 7 , respectively. x cout sub clock output output reset reset i/o i/o an n-channel open-drain i/o pin fo r a system reset. when the srst instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the reset pin outputs ?l? level. d 0 ? d 5 i/o port d (input is examined by skip decision.) i/o each pin of port d has an independent 1-bit wide i/o function. the output structure can be switched to n-channel open-drain or cm os by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. port d 5 is also used as int pin. d 6 , d 7 output port d output each pin of port d has an independent 1-bit wide output function. the output structure is n-channel open-drain. ports d 6 and d 7 are also used as x cin pin and x cout pin, respectively. p0 0 ? p0 3 i/o port p0 i/o port p0 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. po rt p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p0 0? p0 3 are also used as seg 16? seg 19 , respectively. p1 0 ? p1 3 i/o port p1 i/o port p1 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. po rt p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p1 0? p1 3 are also used as seg 20? seg 23 , respectively. p2 0 ? p2 3 i/o port p2 i/o port p2 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. po rt p2 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p2 0? p2 3 are also used as seg 24? seg 27 , respectively. p3 0 ? p3 3 i/o port p3 i/o port p3 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to ?1? and select the n-channel open-drain. po rt p3 has a key-on wakeup function and a pull-up function. both functions can be switched by software. ports p3 0? p3 3 are also used as seg 28? seg 31 , respectively. c output port c output 1-bit output port. the output structur e is cmos. port c is also used as cntr pin. com 0 ? com 3 common output output lcd common output pins. pins com 0 and com 1 are used at 1/2 duty, pins com 0? com 2 are used at 1/3 duty and pins com 0? com 3 are used at 1/4 duty. seg 0 ? seg 31 segment output output lcd segment output pins. seg 0? seg 2 pins are used as v lc3? v lc1 pins, respectively. seg 16? seg 31 pins are used as ports p0 0? p0 3, ports p1 0? p1 3 , ports p2 0? p2 3 , and ports p3 0? p3 3 , respectively. cntr timer i/o i/o cntr pin has the function to input the clock for the timer 1 event counter and to output the pwm signal generated by timer 2. cntr pin is also used as port c. int interrupt input input int pin accepts external interrupts. they have the key-on wak eup function which can be switched by software. int pin is also used as port d 5 . v lc3 ? v lc1 lcd power source ? these are the lcd power supply pins. if an internal resistor is used, connect the v lc3 pin to the v dd pin. (if brightness adjustment is required, connect via a resistor.) when using an external power supply, apply voltage such that v ss v lc1 v lc2 v lc3 v dd . pins v lc3 to v lc1 also function as pins seg 0 to seg 2 .
rev.1.04 aug 23, 2007 page 6 of 146 rej03b0188-0104 4559 group multifunction note 1. pins except above have just single function. note 2. the input/output of d 5 can be used even when int is selected. be careful when using inputs of both int and d 5 since the input threshold value of int pin is different from that of port d 5 . note 3. ?h? output function of port c can be used even when the cntr (output) is used. port function table 4 pin description pin multifunction pin multifunction pin multifunction pin multifunction p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 p2 3 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 seg 24 seg 25 seg 26 seg 27 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 p2 3 p3 0 p3 1 p3 2 p3 3 d 5 d 6 d 7 c seg 0 seg 1 seg 2 seg 28 seg 29 seg 30 seg 31 int x cin x cout cntr v lc3 v lc2 v lc1 seg 28 seg 29 seg 30 seg 31 int x cin x cout cntr v lc3 v lc2 v lc1 p3 0 p3 1 p3 2 p3 3 d 5 d 6 d 7 c seg 0 seg 1 seg 2 table 5 port function port pin input output output structure i/o unit control instructions control registers remark port d d 0 ? d 4 , d 5 / int i/o (6) n-channel open-drain/ cmos 1 bit sd, rd szd, cld fr1, fr2, i1, k2 programmable output structure selection function d 6 /x cin , d 7 /x cout output (2) n-channel open-drain rg ? port p0 p0 0 /seg 16 , p0 1 /seg 17 , p0 2 /seg 18 , p0 3 /seg 19 i/o (4) n-channel open-drain/ cmos 4 bits op0a iap0 pu0, k0, fr0, c1 programmable pull-up, key- on wakeup and output structure selection function port p1 p1 0 /seg 20 , p1 1 /seg 21 , p1 2 /seg 22 , p1 3 /seg 23 i/o (4) n-channel open-drain/ cmos 4 bits op1a iap1 pu1, k0, fr0, c2 programmable pull-up, key- on wakeup and output structure selection function port p2 p2 0 /seg 24 , p2 1 /seg 25 , p2 2 /seg 26 , p2 3 /seg 27 , i/o (4) n-channel open-drain/ cmos 4 bits op2a iap2 pu2, k1, fr3, l3 programmable pull-up, key- on wakeup and output structure selection function port p3 p3 0 /seg 28 , p3 1 /seg 29 , p3 2 /seg 30 , p3 3 /seg 31 i/o (4) n-channel open-drain/ cmos 4 bits op3a iap3 pu3, k2, k3, fr2, c3 programmable pull-up, key- on wakeup and output structure selection function port c c/cntr output (1) cmos 1 bit rcp scp w1, w2, w4 ?
rev.1.04 aug 23, 2007 page 7 of 146 rej03b0188-0104 4559 group definition of clock and cycle ? operation source clock the operation source clock is the source clock to operate this product. in this product, the following clocks are used. ? clock (f(x in )) by the external ceramic resonator ? clock (f(x in )) by the external rc oscillation ? clock (f(x in )) by the external input ? clock (f(ring)) of the on-chip oscillator which is the internal oscillator ? clock (f(x cin )) by the external quartz-crystal oscillation ? system clock (stck) the system clock is the basic cl ock for controlling this product. the system clock is selected by the clock control register mr shown as the table below. ? machine cycle the machine cycle is the standard cycle required to execute the instruction. ? instruction clock (instck) the instruction clock is the basi c clock for controlling cpu. the instruction clock (instck) is a signal derived by dividing the system clock (stck) by 3. the one instruction clock cycle generates the one machine cycle. note 1. the f(ring)/8 is selected after system is released from reset table 6 table selection of system clock register mr system clock operation mode mr 3 mr 2 mr 1 mr 0 1 1 0 0 f(stck) = f(ring)/8 inter nal frequency divided by 8 mode 1 0 0 0 f(stck) = f(ring)/4 inter nal frequency divided by 4 mode 0 1 0 0 f(stck) = f(ring)/2 inter nal frequency divided by 2 mode 0 0 0 0 f(stck) = f(ring) internal frequency through mode 1 1 0 1 f(stck) = f(x in )/8 high-speed frequency divided by 8 mode 1 0 0 1 f(stck) = f(x in )/4 high-speed frequency divided by 4 mode 0 1 0 1 f(stck) = f(x in )/2 high-speed frequency divided by 2 mode 0 0 0 1 f(stck) = f(x in ) high-speed through mode 1 1 1 0 f(stck) = f(x cin )/8 low-speed frequency divided by 8 mode 1 0 1 0 f(stck) = f(x cin )/4 low-speed frequency divided by 4 mode 0 1 1 0 f(stck) = f(x cin )/2 low-speed frequency divided by 2 mode 0 0 1 0 f(stck) = f(x cin ) low-speed through mode
rev.1.04 aug 23, 2007 page 8 of 146 rej03b0188-0104 4559 group connections of unused pins (note when connecting to v ss or v dd ) connect the unused pins to v ss using the thickest wire at the shortest distance against noise. table 7 port function pin connection usage condition x in connect to v ss . rc oscillator is not selected x out open. ? x cin /d 6 connect to v ss . ? x cout /d 7 open. ? d 0 ? d 4 open. ? connect to v ss . n-channel open-drain is selected for the output structure. d 5 /int open. int pin input is disabled. connect to v ss . n-channel open-drain is selected for the output structure. p0 0 / seg 16 ? p0 3 / seg 19 open. the key-on wakeup function is invalid. connect to v ss . segment output is not selected. n-channel open-drain is selected for the output structure. pull-up transistor is off. the key-on wakeup function is invalid. p1 0 / seg 20 ? p1 3 / seg 23 open. the key-on wakeup function is invalid. connect to v ss . segment output is not selected. n-channel open-drain is selected for the output structure. pull-up transistor is off. the key-on wakeup function is invalid. p2 0 / seg 24 ? p2 3 / seg 27 open. the key-on wakeup function is invalid. connect to v ss . segment output is not selected. n-channel open-drain is selected for the output structure. pull-up transistor is off. the key-on wakeup function is invalid. p3 0 / seg 28 ? p3 3 / seg 31 open. the key-on wakeup function is invalid. connect to v ss . segment output is not selected. n-channel open-drain is selected for the output structure. pull-up transistor is off. the key-on wakeup function is invalid. c/cntr open. cntr input is not selected for timer 1 count source. com 0? com 3 open. ? seg 0 /v lc3 open. seg 0 pin is selected. seg 1 /v lc2 open. seg 1 pin is selected. seg 2 /v lc1 open. seg 2 pin is selected. seg 3? seg 15 open. ?
rev.1.04 aug 23, 2007 page 9 of 146 rej03b0188-0104 4559 group port block diagram fig 3. port block diagram (1) fr2 0 d 4 (note 2) s r q notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. i represents bits 0 to 3. 4. as for details, refer to the external interrupt structure. register y decoder skip decision szd instruction sd instruction rd instruction cld instruction fr1i (note 1) d 0 ? d 3 (note 2) s r q d 5 /int(note 2) external 0 interrupt external 0 interrupt circuit key-on wakeup input timer 1 count start synchronous circuit input fr2 1 s r q (note 1) (note 1) (note 1) (note 1) (note 1) (note 3) register y decoder skip decision szd instruction sd instruction rd instruction cld instruction register y decoder skip decision szd instruction sd instruction rd instruction cld instruction (note 4)
rev.1.04 aug 23, 2007 page 10 of 146 rej03b0188-0104 4559 group fig 4. port block diagram (2) x cin /d 6 (note 2) s r q rg 2 1 0 x cout /d 7 (note 2) s r q rg 2 1 0 quartz-crystal oscillation circuit sub-clock input rg 2 c/cntr (note 2) scp instruction rcp instruction s r q pwmod d t q r timer 1 underflow signal w4 1 w1 2 w1 0 w1 1 clock input for timer 1 event count notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. register y decoder sd instruction rd instruction cld instruction (note 1) (note 1) register y decoder sd instruction rd instruction cld instruction (note 1) (note 1) (note 1) (note 1)
rev.1.04 aug 23, 2007 page 11 of 146 rej03b0188-0104 4559 group fig 5. port block diagram (3) k0 1 a k a k d t q fr0 1 pu0 k c1 k c1 k 01 edge detection circuit key-on wakeup input iap0 instruction op0a instruction p0 0 /seg 16 , p0 1 /seg 17 (note 2) k0 0 a j register a a j (note 3) d t q fr0 0 pu0 j pull-up transistor c1 j lcd power supply lcd control signal c1 j 01 p0 2 /seg 18 , p0 3 /seg 19 (note 2) (note 3) lcd power supply (note 3) (note 3) (note 1) (note 1) edge detection circuit key-on wakeup input iap0 instruction op0a instruction register a pull-up transistor lcd power supply lcd control signal lcd power supply (note 4) (note 1) (note 1) (note 4) (note 4) (note 4) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3.
rev.1.04 aug 23, 2007 page 12 of 146 rej03b0188-0104 4559 group fig 6. port block diagram (4) k0 3 a k a k d t q fr0 3 pu1 k c2 k c2 k 01 p1 0 /seg 20 , p1 1 /seg 21 (note 2) k0 2 a j a j d t q fr0 2 pu1 j c2 j c2 j 01 p1 2 /seg 22 , p1 3 /seg 23 (note 2) edge detection circuit key-on wakeup input iap1 instruction op1a instruction register a (note 3) pull-up transistor lcd power supply lcd control signal (note 3) lcd power supply (note 3) (note 3) (note 1) (note 1) edge detection circuit iap1 instruction op1a instruction register a (note 4) pull-up transistor lcd power supply lcd control signal (note 4) lcd power supply (note 4) (note 1) (note 1) (note 4) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. key-on wakeup input
rev.1.04 aug 23, 2007 page 13 of 146 rej03b0188-0104 4559 group fig 7. port block diagram (5) k1 k a k a k d t q fr3 k pu2 k l3 k l3 k 01 p2 0 /seg 24 , p2 1 /seg 25 (note 2) k1 j a j a j d t q fr3 j pu2 j l3 j l3 j 01 p2 2 /seg 26 , p2 3 /seg 27 (note 2) edge detection circuit key-on wakeup input iap2 instruction op2a instruction register a (note 3) pull-up transistor lcd power supply lcd control signal lcd power supply (note 3) (note 3) (note 1) (note 1) edge detection circuit iap2 instruction op2a instruction register a (note 4) pull-up transistor lcd power supply lcd control signal (note 4) lcd power supply (note 4) (note 1) (note 1) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. (note 3) (note 4) key-on wakeup input
rev.1.04 aug 23, 2007 page 14 of 146 rej03b0188-0104 4559 group fig 8. port block diagram (6) k2 3 a k a k d t q fr2 3 pu3 k c3 k c3 k 01 p3 0 /seg 28 , p3 1 /seg 29 (note 2) k2 2 a j a j d t q fr2 2 pu3 j c3 j c3 j 01 p3 2 /seg 30 , p3 3 /seg 31 (note 2) 0 1 0 1 k3 2 k3 3 0 1 0 1 k3 0 k3 1 edge detection circuit key-on wakeup input iap3 instruction op3a instruction register a pull-up transistor lcd power supply lcd control signal lcd power supply (note 3) (note 3) (note 1) (note 1) (note 3) edge detection circuit (note 3) edge detection circuit iap3 instruction op3a instruction register a pull-up transistor lcd power supply lcd control signal lcd power supply (note 4) (note 4) (note 1) (note 1) (note 4) edge detection circuit (note 4) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. 3. j represents bits 0, 1. 4. k represents bits 2, 3. 5. for setting key-on wakeup of ports p3 0 and p3 1 to be invalid (k2 2 = ?0?) set registers k3 0 and k3 1 to ?0.? 6. for setting key-on wakeup of ports p3 2 and p3 3 to be invalid (k2 3 = ?0?) set registers k3 2 and k3 3 to ?0.? key-on wakeup input (note 5) (note 6) (note 5) (note 5) (note 6) (note 6)
rev.1.04 aug 23, 2007 page 15 of 146 rej03b0188-0104 4559 group fig 9. port block diagram (7) seg 3 ? seg 15 (note 2) com 0 ? com 3 (note 2) lcd power supply lcd control signal (note 1) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. lcd control signal lcd power supply (note 1) lcd power supply lcd control signal (note 1) lcd control signal lcd power supply (note 1) lcd power supply lcd control signal lcd control signal
rev.1.04 aug 23, 2007 page 16 of 146 rej03b0188-0104 4559 group fig 10. port block diagram (8) l2 2 01 seg 1 /v lc2 (note 2) l2 1 01 seg 2 /v lc1 (note 2) l2 2 0 1 l2 2 0 1 l1 3 l2 1 0 1 l2 1 0 1 l2 0 0 1 l1 3 0 1 l1 1 0 1 l2 0 l2 0 l1 2 reset signal epof instruction + pof instruction 0 1 l1 3 lcd power supply (v lc3 ) 0 1 l2 3 l2 3 (note 1) l2 3 01 seg 0 /v lc3 (note 2) notes 1. this symbol represents a parasitic diode on the port. 2. applied potential to these ports must be v dd or less. lcd control signal lcd power supply lcd power supply lcd power supply (v lc2 ) lcd power supply (v lc1 ) lcd control signal lcd power supply lcd power supply (note 1) (note 1) (note 1) (note 1) (note 1) lcd control signal lcd power supply lcd power supply
rev.1.04 aug 23, 2007 page 17 of 146 rej03b0188-0104 4559 group fig 11. external interrupt circuit structure key-on wakeup input snzi0 instruction (note 1) k2 1 0 1 edge detection circuit level detection circuit d 5 /int i1 3 i1 2 falling 0 1 rising k2 0 i1 1 0 1 one-sided edge detection circuit both edges detection circuit skip decision exf0 external 0 interrupt timer 1 count start synchronization circuit input (note 2) (note 3) notes 1: this symbol represents a parasitic diode on the port. 2: when i1 2 is 0, ?l? level is detected. when i1 2 is 1, ?h? level is detected. 3: when i1 2 is 0, falling edge is detected. when i1 2 is 1, rising edge is detected. (note 1) or
rev.1.04 aug 23, 2007 page 18 of 146 rej03b0188-0104 4559 group function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4-bit data addition, comparison , and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, exchange, and i/o operation. carry flag cy is a 1-bit flag that is set to ?1? when there is a carry with the amc instruction (figure 12). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (figure 13). carry flag cy can be set to ?1? with the sc instruction and cleared to ?0? with the rc instruction. (3) registers b and e register b is a 4-bit register us ed for temporary storage of 4-bit data, and for 8-bit data transf er together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 14). register e is undefined after syst em is released from reset and returned from the power down mode . accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruct ion is executed (figure 15). also, when the tabp p instruction is executed at uptf flag = ?1?, the high-order 2 bits of rom reference data is stored to the low-order 2 bits of regi ster d, the high-order 1 bit of register d is ?0?. when the tabp p instruction is executed at uptf flag = ?0?, the contents of register d remains unchanged. the uptf flag is set to ?1? with the supt instruction and cleared to ?0? with the rupt instruction. the initial value of uptf flag is ?0?. register d is undefined after syst em is released from reset and returned from the power down mode . accordingly, set the initial value. fig 12. amc instruction execution example fig 13. rar instruction execution example fig 14. registers a, b and register e fig 15. tabp p instruction execution example (cy) (m(dp)) (a) addition alu rc instruction sc instruction cy a 3 a 2 a 1 a 0 rar instruction a 0 cy a 3 a 2 a 1 tabe instruction teab instruction a 3 a 2 a 1 a 0 register a tab instruction e 3 e 2 e 1 e 0 e 7 e 6 e 5 e 4 b 3 b 2 b 1 b 0 register b register e a 3 a 2 a 1 a 0 register a tba instruction b 3 b 2 b 1 b 0 register b a 3 a 2 a 1 a 0 dr 2 dr 1 dr 0 pc l register a (4) low-order 2 bits register d (3) register b (4) middle-order 2 bits rom field value p the contents of register d specifying address tabp p instruction p 3 p 2 p 1 p 0 p 6 p 5 p 4 pc h 840 the contents of register a high-order 2 bits flag uptf = 1; high-order 2 bits of reference data is transferred to the low-order 2 bits of register d. ?0? is stored to the high-order 1 bit of register d. flag uptf = 0; data is not transferred to register d.
rev.1.04 aug 23, 2007 page 19 of 146 rej03b0188-0104 4559 group (5) stack registers (sks) and stack pointer (sp) stack registers are 14-bit registers. stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; ? branching to an interrupt service routine (referred to as an interrupt service routine), ? performing a subroutine call, or ? executing the table refere nce instruction (tabp p). stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be careful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 levels are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 16 shows the stack registers (sks) structure. figure 17 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an interrupt occurs, this register (s dp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and register b just before an interr upt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table reference instruction. (7) skip flag skip flag controls skip deci sion for the conditional skip instructions and cont inuous described skip instructions. when an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig 16. stack registers (sks) structure fig 17. example of operation at subroutine call program counter (pc) sk 0 sk 1 sk 2 sk 3 sk 4 sk 5 sk 6 sk 7 (sp) = 0 (sp) = 1 (sp) = 2 (sp) = 3 (sp) = 4 (sp) = 5 (sp) = 6 (sp) = 7 stack pointer (sp) points ?7? at reset or returning from power down mode. it points ?0? by executing the first bm instruction, and the contents of program counter is stored in sk 0 . when the bm instruction is executed after eight stack registers are used ((sp) = 7), (sp) = 0 and the contents of sk 0 is destroyed. executing bm instruction executing rt instruction (sp) 0 (sk 0 ) 0001 16 (pc) sub1 (pc) (sk 0 ) (sp) 7 main program address 0000 16 nop 0001 16 bm sub1 0002 16 nop sub1: nop rt subroutine note :returning to the bm instruction execution address with the rt instruction, and the bm instruction becomes the nop instruction. . . .
rev.1.04 aug 23, 2007 page 20 of 146 rej03b0188-0104 4559 group (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a bi nary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call inst ructions, return instructions, or the table reference instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which specifies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 18). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, register x specifies a file, and register y specifies a ram digit (figure 19). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd , or szd instruction (figure 20). ?note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the power down mode. after system is returned from the power down mode, set these registers. fig 18. program counter (pc) structure fig 19. data pointer (dp) structure fig 20. sd instruction execution example a 3 a 2 a 1 a 0 a 6 a 5 a 4 pc h specifying page program counter (pc) p 3 p 2 p 1 p 0 p 6 p 5 p 4 pc l specifying address register y (4) data pointer (dp) x 2 x 1 x 0 y 3 z 1 z 0 x 3 y 2 y 1 y 0 register x (4) register z (2) specifying ram digit specifying ram file specifying ram file group specifying bit position 0 0 0 1 register y (4) set d 3 d 2 1 d 1 d 0 port d output latch
rev.1.04 aug 23, 2007 page 21 of 146 rej03b0188-0104 4559 group program memory (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. figure 21 shows the rom map of m34559g6. a part of page 1 (addresses 0080 16 to 00ff 16 ) is reserved for interrupt addresses (figure 22). when an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and th e instruction at the interrupt address is executed. when usin g an interrupt service routine, write the instruction generating th e branch to that routine at an interrupt address. page 2 (addresses 0100 16 to 017f 16 ) is the special page for subroutine calls. subroutines writ ten in this page can be called from any page with the 1-word instruction (bm). subroutines extending from page 2 to another pa ge can also be called with the bm instruction when it starts on page 2. rom pattern (bits 9 to 0) of al l addresses can be used as data areas with the tabp p instruction. rom code protect address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by renesas technology corp., read ing or writing from/to qzrom is disabled by a serial programmer. as for the qzrom product in blan k, the rom code is protected by selecting the protect bit wr ite at rom writing with a serial programmer. as for the qzrom product shippe d after writing, whether the rom code protect is used or not can be selected as rom option setup (?mask option? written in the mask file converter) when ordering. fig 21. rom map of m34559g6 fig 22. page 1 (addresses 0080 16 to 00ff 16 ) structure table 8 rom size and pages part number rom (prom) size ( 10 bits) pages m34559g6 6144 words 48 (0 to 47) interrupt address page subroutine special page 0000 16 007f 16 0080 16 00ff 16 0100 16 017f 16 0180 16 17ff 16 page 47 page 0 page 1 page 2 page 3 9876543210 00ff 16 008c 16 008a 16 0088 16 timer 2 interrupt address 0086 16 timer 1 interrupt address 0084 16 0082 16 external 0 interrupt address 0080 16 9876543210 timer 3 interrupt address
rev.1.04 aug 23, 2007 page 22 of 146 rej03b0188-0104 4559 group data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram ad dress is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram (also, set a value after system returns from power down mode). ram includes the area for lcd. when writing ?1? to a bit corresponding to displayed segment, the segment is turned on. table 9 shows the ram size. figure 23 shows the ram map. ?note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in power down mode. after system is returned from the power down mode, set these registers. fig 23. ram map table 9 ram size and pages part number ram size m34559g6 288 words 4 bits (1152 bits) register z register y register x 0 0 1 2 3 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ram 288 words 4 bits (1152 bits) 13 14 15 0 1 2 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 note: the numbers in the shaded area indicate the corresponding segment output pin numbers. ...
rev.1.04 aug 23, 2007 page 23 of 146 rej03b0188-0104 4559 group interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt addr ess) according to each interrupt source. an interrupt occurs when the foll owing 3 cond itions are satisfied. ? an interrupt activated condition is satisfied (request flag = ?1?) ? interrupt enable bit is enabled (?1?) ? interrupt enable flag is enabled (inte = ?1?) table 10 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (in te) controls whether the every interrupt enable/disable. interrupts are enabled when inte flag is set to ?1? with the ei instru ction and disabled when inte flag is cleared to ?0? with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to ?0,? so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 11 shows the interrupt reques t flag, interrupt enable bit and skip instruction. table 12 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to ?1.? each interrupt request flag except the voltage dr op detection circuit interrupt request flag is cleared to ?0? when either; ? an interrupt occurs, or ? a skip instruction is executed. the voltage drop detection circu it interrupt request flag cannot be cleared to ?0? at the state that the activated condition is satisfied. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its interrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one inte rrupt request flag is set when the interrupt disable state is released, the interru pt priority leve l is as follows shown in table 10. table 10 interrupt sources priority level interrupt source interrupt address interrupt name activated condition 1 external 0 interrupt level change of int0 pin address 0 in page 1 2 timer 1 interrupt timer 1 underflow address 4 in page 1 3 timer 2 interrupt timer 2 underflow address 6 in page 1 4 timer 3 interrupt timer 3 underflow address 8 in page 1 table 11 interrupt request flag, interrupt enable bit and skip instruction interrupt name interrupt request flag skip instruction interrupt enable bit external 0 interrupt exf0 snz0 v1 0 timer 1 interrupt t1f snzt1 v1 2 timer 2 interrupt t2f snzt2 v1 3 timer 3 interrupt t3f snzt3 v2 0 table 12 interrupt en able bit function interrupt enable bit occurrence of interrupt skip instruction 1 enabled invalid 0 disabled valid
rev.1.04 aug 23, 2007 page 24 of 146 rej03b0188-0104 4559 group (4) internal state during an interrupt the internal state of the microcom puter during an interrupt is as follows (figure 25). ? program counter (pc) an interrupt address is set in program c ounter. the address to be executed when returnin g to the main routine is automatically stored in the stack register (sk). ? interrupt enable flag (inte) inte flag is cleared to ?0? so that interrupts are disabled. ? interrupt request flag only the request flag for the curre nt interrupt source is cleared to ?0?. ? data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt o ccurs, a program at an interrupt address is executed after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an interrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing th e ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interr upts are enabled after returning the main routine. (refer to figure 24) fig 24. program example of interrupt processing fig 25. internal state when interrupt occurs fig 26. interrupt system diagram main routine interrupt occurs interrupt is enabled interrupt service routine ei rti : interrupt enabled state : interrupt disabled state each interrupt address ? program counter (pc) the address of main routine to be executed when returning ? stack register (sk) 0 (interrupt disabled) ? interrupt enable flag (inte) 0 ? interrupt request flag (only the flag for the current interrupt source) stored in the interrupt stack register (sdp) automatically ? data pointer, carry flag, registers a and b, skip flag request flag (state retained) enable bit enable flag timer 2 underflow t1f v1 2 address 4 in page 1 timer 1 underflow t2f v1 3 address 6 in page 1 t3f v2 0 address 8 in page 1 activated condition inte timer 3 underflow exf0 v1 0 address 0 in page 1 int pin interrupt waveform input
rev.1.04 aug 23, 2007 page 25 of 146 rej03b0188-0104 4559 group (6) interrupt control registers ? interrupt control register v1 interrupt enable bits of extern al 0, timer 1 and timer 2 are assigned to register v1. set the co ntents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. ? interrupt control register v2 the timer 3 interrupt enable bit are assigned to register v2. set the contents of this register through register a with the tv2a instruction. the tav2 instructi on can be used to transfer the contents of register v2 to register a. note 1.?r? represents read enabled, and ?w? represents write enabled. (7) interrupt sequence interrupts occur only when th e respective inte flag, interrupt enable bits (v1 0 , v1 2 , v1 3 , v3 0 ), and interrupt request flag are set to ?1. ? the interrupt occurs two or three cycles after the cycle where all the above three conditions are satisfied. the interrupt occurs after three machine cycles if instructions other than one-cycle instruction are executed when the conditions are satisfied (refer to figure 27). table 13 interrupt control registers interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w tav1/tv1a v1 3 timer 2 interrupt enable bit 0 interrupt disabled (snzt2 instruction is valid) 1 interrupt enabled (snzt2 instruction is invalid) v1 2 timer 1 interrupt enable bit 0 interrupt disabled (snzt1 instruction is valid) 1 interrupt enabled (snzt1 instruction is invalid) v1 1 not used 0 this bit has no function, but read/write is enabled. 1 v1 0 external 0 interrupt enable bit 0 interrupt disabled (snz0 instruction is valid) 1 interrupt enabled (snz0 instruction is invalid) interrupt control register v2 at reset : 0000 2 at power down : 0000 2 r/w tav2/tv2a v2 3 not used 0 this bit has no function, but read/write is enabled. 1 v2 2 not used 0 this bit has no function, but read/write is enabled. 1 v2 1 not used 0 this bit has no function, but read/write is enabled. 1 v2 0 timer 3 interrupt enable bit 0 interrupt disabled (snzt3 instruction is valid) 1 interrupt enabled (snzt3 instruction is invalid)
rev.1.04 aug 23, 2007 page 26 of 146 rej03b0188-0104 4559 group fig 27. interrupt sequence t 3 t 2 t 1 1 machine cycle system clock (stck) interrupt enable flag (inte) int t1f t2f t3f the program starts from the interrupt address. interrupt activated condition is satisfied. flag cleared 2 to 3 machine cycles (notes 1, 2) exf0 external 0 interrupt timer 1 timer 2 timer 3 interrupt when an interrupt request flag is set after its interrupt is enabled ei instruction execution cycle interrupt enabled state interrupt disabled state retaining level of system clock for 4 periods or more is necessary. notes 1: the address is stacked to the last cycle. 2: this interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. t 3 t 2 t 1 t 3 t 2 t 1 t 3 t 2 t 1 t 2 t 1
rev.1.04 aug 23, 2007 page 27 of 146 rej03b0188-0104 4559 group external interrupts the 4559 group has the external 0 interrupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be cont rolled with the interrupt control register i1. fig 28. external interrupt circuit structure table 14 external interrupt activated conditions name input pin activated condition valid waveform selection bit external 0 interrupt d 5 /int when the next waveform is input to d 5 /int pin ? falling waveform ( ? h ? ? l ? ) ? rising waveform ( ? l ? ? h ? ) ? both rising and falling waveforms i1 1 i1 2 key-on wakeup input snzi0 instruction (note 1) k2 1 0 1 edge detection circuit level detection circuit d 5 /int i1 3 i1 2 falling 0 1 rising k2 0 i1 1 0 1 one-sided edge detection circuit both edges detection circuit skip exf0 external 0 interrupt timer 1 count start synchronization circuit input (note 2) (note 3) note 1: this symbol represents a parasitic diode on the port. 2: when i1 2 = 0(x=0 or 1) is 0, ?l? level is detected. when i1 2 is 1, ?h? level is detected. 3: when i1 2 is 0, falling edge is detected. when i1 2 is 1, rising edge is detected. (note 1) or
rev.1.04 aug 23, 2007 page 28 of 146 rej03b0188-0104 4559 group (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to ?1? when a valid waveform is input to d 5 /int pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 27). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt contro l register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to ?0? when an interrupt occurs or when the next instruction is skipped with the skip instruction. ? external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to d 5 /int pin. the valid waveform can be sele cted from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the extern al 0 interrupt is as follows. (1) set the bit 3 of register i1 to ?1? for the int pin to be in the input enabled state. (2) select the valid waveform with the bits 1 and 2 of register i1. (3) clear the exf0 flag to ?0? with the snz0 instruction. (4) set the nop instruction for the case when a skip is performed with the snz0 instruction. (5) set both the external 0 interrupt enable bit (v1 0 ) and the inte flag to ?1.? the external 0 interrupt is now enabled. now when a valid waveform is input to the d 5 /int pin, the exf0 flag is set to ?1? and the external 0 interrupt occurs. (2) external interrupt control registers (1) interrupt cont rol register i1 register i1 controls the valid waveform for the external 0 interrupt. set the contents of th is register through register a with the ti1a instruction. th e tai1 instruction can be used to transfer the contents of register i1 to register a. note 1.?r? represents read enabled, and ?w? represents write enabled. note 2.when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. table 15 external interrupt control register interrupt control register i1 at reset : 0000 2 at power down : state retained r/w tai1/ti1a i1 3 int pin input control bit (note 2) 0 int pin input disabled 1 int pin input enabled i1 2 interrupt valid waveform for int pin/ return level selection bit (note 2) 0 falling waveform (?l? level of int pin is recognized with the snzi0 instruction)/?l? level 1 rising waveform (?h? level of int pin is recognized with the snzi0 instruction)/?h? level i1 1 int pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i1 0 int pin timer 1 count start synchronous circuit selection bit 0 timer 1 count start synchronous circuit not selected 1 timer 1 count start synchronous circuit selected
rev.1.04 aug 23, 2007 page 29 of 146 rej03b0188-0104 4559 group (3) notes on interrupts (1) bit 3 of register i1 when the input of the int pin is controlled with the bit 3 of register i1 in software, be ca reful about the following notes. ? depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 29.) and then, change the bit 3 of register i1. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at least one instruction (refer to (2) in figure 29.). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 29.). fig 29. external 0 interrupt program example-1 (2) bit 3 of register i1 when the bit 3 of register i1 is cleared to ?0?, the power down mode is selected and the input of int pin is disabled, be careful about the following notes. ? when the int pin input is disabled (register i1 3 = ?0?), set the key-on wakeup of int pin to be invalid (register k2 0 = ?0?) before system enters to power down mode. (refer to (1) in figure 30.). fig 30. external 0 interrupt program example-2 (3) bit 2 of register i1 when the interrupt valid wa veform of the int pin is changed with the bit 2 of regist er i1 in software, be careful about the following notes. ? depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 31.) and then, cha nge the bit 2 of register i1 is changed. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at least one instruction (refer to (2) in figure 31.). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 31.). fig 31. external 0 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int pin input is changed nop ...................................................... (2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tk2a ; int0 key-on wakeup disabled .....(1) di epof pof2 ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ......(1) la 12 ; ( 1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.04 aug 23, 2007 page 30 of 146 rej03b0188-0104 4559 group timers the 4559 group has the following timers. ? programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be se t. it is decremented from a setting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to ?1,? new data is loaded from the reload register, and count cont inues (auto-reload function). ? fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency dividing ratio (n). an interrupt request flag is set to ?1? after every n count of a count pulse. fig 32. auto-reload function n+1 count reload n+1 count an interrupt occurs or a skip instruction is executed. 1st underflow reload 2nd underflow ff 16 time n 00 16 ?1? ?0? n : counter initial value the contents of counter timer interrupt request flag count starts
rev.1.04 aug 23, 2007 page 31 of 146 rej03b0188-0104 4559 group the 4559 group timer consists of the following circuits. ? prescaler : 8-bit programmable timer ? timer 1 : 8-bit programmable timer ? timer 2 : 8-bit programmable timer ? timer 3 : 16-bit fixed frequency timer ? timer lc : 4-bit programmable timer ? watchdog timer: 16-bit fixed frequency timer (timers 1, 2 and 3 have the in terrupt function, respectively) prescaler, timer 1, timer 2, timer 3 and timer lc can be controlled with the timer control registers pa and w1 to w4. the watchdog timer is a free counter wh ich is not controlled with the control register. each function is described below. table 16 function related timers circuit structure count source frequency dividing ratio use of output signal control register prescaler 8-bit programmable binary down counter ? instruction clock (instck) 1 to 256 ? timer 1 count source ? timer 2 count source ? timer 3 count source pa timer 1 8-bit programmable binary down counter (link to int input) (carrier wave output auto- control function) ? pwm signal (pwmout) ? prescaler output (orclk) ? timer 3 underflow (t3udf) ? cntr input 1 to 256 ? cntr output control ? timer 1 interrupt w1 w4 timer 2 8-bit programmable binary down counter (with carrier wave generation function) ?x in input ? prescaler output divided by 2 (orclk/2) 1 to 256 ? timer 1 count source ? cntr output ? timer 2 interrupt w2 w4 timer 3 16-bit fixed dividing frequency ?x in input ? prescaler output (orclk) 8192 16384 32768 65536 ? timer 1 count source ? timer lc count source ? timer 3 interrupt w3 timer lc 4-bit programmable binary down counter ? bit 4 of timer 3 (t3 4 ) ? system clock (stck) 1 to 16 ? lcd clock w4 watchdog timer 16-bit fixed dividing frequency ? instruction clock (instck) 65536 ? system reset (counting twice) ? decision of flag wdf1 -
rev.1.04 aug 23, 2007 page 32 of 146 rej03b0188-0104 4559 group fig 33. timers structure (1) x in orclk x in orclk w2 1 timer 2 (8) reload register r2l (8) register b (tab2) (t2ab) register a (t2ab) (t2ab) (tab2) timer 2 interrupt 11 10 01 00 w1 1 , w1 0 pwmout orclk w1 2 w4 0 0 1 timer 1 (8) reload register r1 (8) register b (tab1) (t1ab) register a (t1ab) (t1ab) (tab1) t1f timer 1 interrupt timer 1 underflow signal (t1udf) t3udf 00 01 10 11 mr 3 , mr 2 division circuit divided by 8 divided by 4 divided by 2 internal clock generating circuit (divided by 3) system clock (stck) instruction clock (instck) prescaler (8) pa 0 reload register rps (8) register b (tabps) (tpsab) register a (tpsab) (tpsab) (tabps) (tr1ab) 10 01 (crck) mr 1 , mr 0 on-chip oscillator quartz-crystal oscillation x cin multi- plexer ceramic resonance rc oscillation d 5 /int i1 3 i1 2 0 1 i1 1 0 1 one-sided edge detection circuit both edges detection circuit s r q i1 0 w1 3 t1udf c/cntr w1 1 w1 0 pwmout q d r t w1 2 w4 1 t1udf i1 0 1 0 port c output w2 0 0 1 reload register r2h (8) register b register a reload control circuit ?h? interval expansion w2 2 1 0 (t2r2l) (t2hab) t2f q r t w2 3 pwmod data is set automatically from each reload register when timer underflows (auto-reload function). 1/2 00
rev.1.04 aug 23, 2007 page 33 of 146 rej03b0188-0104 4559 group fig 34. timers structure (2) watchdog reset signal reset signal (note 2) d t q r dwdt instruction + wrst instruction reset signal (note 3) (note 1) wrst instruction watchdog timer (16) 1 - - - - - - - - - - - - - 16 instck s r q wdf1 s r q wef note 1: flag wdf1 is cleared to ?0? and the next instruction is skipped when the wrst instruction is executed while flag wdf1 = ?1?. the wrst instruction is equivalent to the nop instruction while flag wdf1 = ?0?. 2: flag wef is cleared to ?0? and watchdog timer reset does not occur when the dwdt instruction and wrst instruction are executed continuously. 3: the wef flag is set to ?1? at system reset or ram back-up mode. data is set automatically from each reload register when timer underflows (auto-reload function). w4 2 0 1 w4 3 timer lc (4) reload register rlc (4) (tlca) (tlca) register a timer 3 interrupt stck t3f timer 3 underflow signal (t3udf) lcd clock 1/2 00 01 10 11 w3 1 , w3 0 timer 3 (16) 1 - - 4 - - - - - 13 14 15 16 w3 3 0 1 w3 2 x cin orclk
rev.1.04 aug 23, 2007 page 34 of 146 rej03b0188-0104 4559 group note 1. ? r ? represents read enabled, and ? w ? represents write enabled. note 2. this function is valid only when the timer 1 control start synchronous circuit is selected (i1 0 = ? 1 ? ). note 3. port c output is invalid when cntr input is selected for the timer 1 count source. table 17 timer control registers timer control register pa at reset : 0 2 at power down : 0 2 w tpaa pa 0 prescaler control bit 0 stop (state retained) 1operating timer control register w1 at reset : 0000 2 at power down : state retained r/w taw1/tw1a w1 3 timer 1 count auto-stop circuit selection bit (note 2) 0 timer 1 count auto-stop circuit not selected 1 timer 1 count auto-stop circuit selected w1 2 timer 1 control bit 0 stop (state retained) 1operating timer 1 count source selection bits (note 3) w1 1 w1 0 count source w1 1 0 0 pwm signal (pwmout) 0 1 prescaler output (orclk) 1 0 timer 3 underflow signal (t3udf) w1 0 1 1 cntr input timer control register w2 at reset : 0000 2 at power down : 0000 2 r/w taw2/tw2a w2 3 cntr pin function control bit 0 cntr pin output invalid 1 cntr pin output valid w2 2 pwm signal ? h ? interval expansion function control bit 0 pwm signal ? h ? interval expansion function invalid 1 pwm signal ? h ? interval expansion function valid w2 1 timer 2 control bit 0 stop (state retained) 1operating w2 0 timer 2 count source selection bit 0x in input 1 prescaler output (orclk)/2 timer control register w3 at reset : 0000 2 at power down : state retained r/w taw3/tw3a w3 3 timer 3 count source selection bit 0x cin input 1 prescaler output (orclk) w3 2 timer 3 control bit 0 stop (initial state) 1operating timer 3 count value selection bits w3 1 w3 0 count value w3 1 0 0 underflow every 8192 count 0 1 underflow every 16384 count 1 0 underflow every 32768 count w3 0 1 1 underflow every 65536 count timer control register w4 at reset : 0000 2 at power down : state retained r/w taw4/tw4a w4 3 timer lc control bit 0 stop (state retained) 1operating w4 2 timer lc count source selection bit 0bit 4 (t3 4 ) of timer 3 1 system clock (stck) w4 1 cntr pin output auto-control circuit selection bit 0 cntr output auto-control circuit not selected 1 cntr output auto-control circuit selected w4 0 cntr pin input count edge selection bit 0 falling edge 1 rising edge
rev.1.04 aug 23, 2007 page 35 of 146 rej03b0188-0104 4559 group (1) timer control registers ? timer control register pa register pa controls the count operation of prescaler. set the contents of this register through register a with the tpaa instruction. ? timer control register w1 register w1 controls the coun t operation and count source of timer 1, and timer 1 count auto-s top circuit. set the contents of this register through register a with the tw1a instruction. the taw1 instruction can be used to transfer the contents of register w1 to register a. ? timer control register w2 register w2 controls the coun t operation and count source of timer 2, cntr pin output, an d extension function of pwm signal ?h? interval. set the cont ents of this re gister through register a with the tw2a instruction. the taw2 instruction can be used to transfer the cont ents of register w2 to register a. ? timer control register w3 register w3 controls the coun t operation and count source of timer 3. set the contents of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the contents of register w3 to register a. ? timer control register w4 register w4 controls the input count edge of cntr pin, cntr1 pin output auto-control circ uit. set the contents of this register through register a with the tw4a instruction. the taw4 instruction can be used to transfer the contents of register w4 to register a. (2) prescaler prescaler is an 8-bit binary down counter with the prescaler reload register prs. data can be set simultaneously in prescaler and the reload register rps with the tpsab instruction. data can be read from reload register rps with the tabps instruction. stop counting and then execute the tpsab or tabps instruction to read or set prescaler data. prescaler starts counting after the following process; (1) set data in prescaler, and (2) set the bit 0 of register pa to ?1.? when a value set in reload register rps is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). count source for prescaler can be selected the instruction clock (instck). once count is started, when pr escaler underflows (the next count pulse is input after the contents of prescaler becomes ?0?), new data is loaded from reload regi ster rps, and count continues (auto-reload function). the output signal (orclk) of pres caler can be used for timer 1, 2 and 3 count sources. (3) timer 1 (inte rrupt function) timer 1 is an 8-bit binary down counter with a timer 1 reload register (r1). data can be set simultaneously in timer 1 and the reload register r1 with the t1ab instruction. data can be read from timer 1 with the tab1 instruction. stop counting and then execute the t1ab or tab1 instruction to read or set timer 1 data. when executing the tr1ab instru ction to set data to reload register r1 while timer 1 is ope rating, avoid a t iming when timer 1 underflows. timer 1 starts counting af ter the following process; (1) set data in timer 1 (2) set count source by bit 0 and 1 of register w1, and (3) set the bit 2 of register w1 to ?1.? when a value set in reload register r1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes ?0?), the timer 1 interrupt request flag (t1f) is set to ?1,? new data is loaded from reload register r1, and count continues (auto-reload function). int pin input can be used as th e start trigger for timer 1 count operation by setting the bit 0 of register i1 to ?1?. also, in this time, the auto-stop function by timer 1 underflow can be performed by se tting the bit 3 of register w1 to ?1.? (4) timer 2 (inte rrupt function) timer 2 is an 8-bit binary down counter with two timer 2 reload register (r2l, r2h). data can be set simultaneously in timer 2 and the reload register r2l with the t2ab instruction. data can be set in the reload register r2h with the t2hab instruction. the contents of reload register r2l set with the t2ab instruction can be set to timer 2 again with the t2r2l instruction. data can be read from timer 2 with the tab2 instruction. stop counting and then execute the t2ab or tab2 instruction to read or set timer 2 data. when executing the t2 hab instruction to set data to reload register r2h while timer 2 is operating, avoid a timing when timer 2 underflows. timer 2 starts counting af ter the following process; (1) set data in timer 2 (2) set count source by bi t 0 of register w2, and (3) set the bit 1 of register w2 to ?1.? when a value set in reload register r2l is n and r2h is m, timer 2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255, m = 0 to 255). once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes ?0?), the timer 2 interrupt request flag (t2f) is set to ?1,? new data is loaded from reload register r2 l, and count continues (auto- reload function). when bit 3 of register w2 is set to ?1?, timer 2 reloads data from reload register r2l and r2 h alternately each underflow. timer 2 generates the pwm si gnal (pwmout) of the ?l? interval set as reload register r2l, and the ?h? interval set as reload registerr2h. the pwm signal (pwmout) is output from cntr pin. when bit 2 of regi ster w2 is set to ?1? at this time, the interval (pwm signal ?h? interval) set to reload register r2h for the counter of timer 2 is extended for a half period of count source. in this case, when a value set in reload register r2h is m, timer 2 divides the count source signal by n + 1.5 (m = 1 to 255). when this function is used, set ?1? or more to reload register r2h.
rev.1.04 aug 23, 2007 page 36 of 146 rej03b0188-0104 4559 group when bit 1 of register w4 is se t to ?1?, the pwm signal output to cntr pin is switched to valid/invalid each timer 1 underflow. however, when timer 1 is stopped (bit 2 of register w1 is cleared to ?0?), this function is canceled. even when bit 1 of a register w2 is cleared to ?0? in the ?h? interval of pwm signal, timer 2 does not stop until it next timer 2 underflow. when clearing bit 1 of register w2 to ?0? to stop timer 2, avoid a timing when timer 2 underflows. (5) timer 3 (interrupt function) timer 3 is a 16-bit binary down counter. timer 3 starts counting af ter the following process; (1) set count value by bits 0 and 1 of register w3, (2) set count source by bit 3 of register w3, and (3) set the bit 2 of register w3 to ?1.? once count is starte d, when timer 3 underflows (the set count value is counted), the timer 3 inte rrupt request flag (t3f) is set to ?1,? and count continues. bit 4 of timer 3 can be used as the timer lc count source for the lcd clock generating. when bit 2 of register w3 is cleared to ?0?, timer 3 is initialized to ?ffff 16 ? and count is stopped. timer 3 can be used as the counter for clock because it can be operated at clock operating mode (pof instruction execution). when timer 3 underflow occurs at clock operating mode, system returns from the power down state. when operating timer 3 during cl ock operating mode, set 1 cycle or more of count source to th e following period; from setting bit 2 of register w3 to ?1? till executing the pof instruction. (6) timer lc timer lc is a 4-bit binary do wn counter with the timer lc reload register (rlc). data can be set simultaneously in timer lc and the reload register (r lc) with the tlca instruction. data cannot be read from timer lc. stop counting and then execute the tlca instruction to set timer lc data. timer lc starts counting af ter the following process; (1) set data in timer lc, (2) select the count source with the bit 2 of register w4, and (3) set the bit 3 of register w4 to ?1.? when a value set in reload register rlc is n, timer lc divides the count source signal by n + 1 (n = 0 to 15). once count is started, when t imer lc underflows (the next count pulse is input after the contents of timer lc becomes ?0?), new data is loaded from reload regi ster rlc, and count continues (auto-reload function). timer lc underflow signal divided by 2 can be used for the lcd clock. (7) timer input/output pin (c/cntr pin) cntr pin is used to input the timer 1 count source and output the pwm signal generated by timer 2. the selection of cntr output signal can be controll ed by bit 3 of register w2. when the pwm signal is output from c/cntr pin, set ?0? to the output latch of port c. when the cntr input is selected for timer 1 count source, timer 1 counts the waveform of cn tr input selected by bit 0 of register w4. also, when the cn tr input is selected, the output of port c is invalid (high-impedance state). (8) timer interrupt request flags (t1f, t2f, t3f) each timer interrupt request flag is set to ?1? when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2, snzt3). use the interrupt control register v1, v2 to select an interrupt or a skip instruction. an interrupt request flag is cl eared to ?0? when an interrupt occurs or when the next instruction is skipped with a skip instruction. (9) count start synchron ization circuit (timer 1) timer 1 has the count start synchronous circuit which synchronizes the input of int pi n, and can start the timer count operation. timer 1 count start synchronous ci rcuit function is selected by setting the bit 0 of register i1 to ?1? and the control by int pin input can be performed. when timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count sour ce is input to timer by inputting valid waveform to int pin. the valid waveform of int pin to set the count start synchronous circuit is the same as the exte rnal interrupt activated condition. once set, the count start s ynchronous circuit is cleared by clearing the bit i1 0 to ?0? or system reset. however, when the count auto-st op circuit is selected, the count start synchronous circuit is clea red (auto-stop) at the timer 1 underflow. (10)count auto-stop circuit (timer 1) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. the count auto-stop circuit is valid by setting the bit 3 of register w1 to ?1?. it is cleared by the timer 1 underflow and the count source to time r 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected.
rev.1.04 aug 23, 2007 page 37 of 146 rej03b0188-0104 4559 group (11) precautions ? prescaler stop prescaler counting and then execute the tabps instruction to read its data. stop prescaler counting and then execute the tpsab instruction to write data to prescaler. ? timer count source stop timer 1, 2, 3 or lc counti ng to change its count source. ? reading the count value stop timer 1 or 2 counting and then execute the tab1 or tab2 instruction to read its data. ? writing to the timer stop timer 1, 2 or lc counting and then execute the t1ab, t2ab, t2r2l or tlca instruction to write data to timer. ? writing to reload register in order to write a data to the reload register r1 while the timer 1 is operating, execute the tr1ab instruction except a timing of the timer 1 underflow. in order to write a data to the reload register r2h while the timer 2 is operating, execute th e t2hab instruction except a timing of the timer 3 underflow. ? pwm signal if the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the pwm signal, a hazard may occur in the pwm output waveform. when ?h? interval expansion f unction of the pwm signal is used, set ?1? or more to reload register r2h. set the port c output latch to ?0? to output the pwm signal from c/cntr pin. ?timer 3 stop timer 3 counting to change its count source. when operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register w3 to ?1? till executing the pof instruction. ? prescaler and timer 1 count st art timing and count time when operation starts count starts from the first rising edge of the count source (2) in figure 35 after prescaler and timer operations start (1) in figure 35. time to first underflow (3) in figu re 35 is shorter (for up to 1 period of the count source) than time among next underflow (4) in figure 35 by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 1, timer 1 operates synchronizing with the falling edge of cntr input. fig 35. timer count start timing and count time when operation starts ? timer 2 and timer lc count start timing and count time when operation starts count starts from the rising edge (2) after the first falling edge of the count source, after ti mer 2 and timer lc operations start (1). time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source operations after count starts. fig 36. timer count start timing and count time when operation starts (timer 2 and timer lc) count source (3) (4) (1) timer start (2) count source (when falling edge of cntr input is selected) timer 1 value timer 1 underflow signal 32 1 0 3 2 1 0 3 2 count source (3) (4) (1) timer start (2) timer value timer underflow signal 3 2 1 0 3 2 1 0 3
rev.1.04 aug 23, 2007 page 38 of 146 rej03b0188-0104 4559 group fig 37. timer 2 operation example timer 2 count source timer 2 start timer 2 count value (reload register) timer 2 underflow signal pwm signal 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 03 16 (r2l) (r2l) (r2l) (r2l) (r2l) pwm1 signal ?l? fixed - cntr pin output invalid (w2 3 =0) timer 2 count source timer 2 start timer 2 count value (reload register) timer 2 underflow signal pwm signal 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 03 16 (r2l) (r2h) (r2l) (r2h) (r2l) (r2h) pwm period 7 clock pwm period 7 clock * : ?03 16 ? is set to reload register r3l and ?02 16 ? is set to reload register r3h. 4 clock 3 clock 4 clock 3 clock 4 clock timer 2 count source timer 2 start timer 2 count value (reload register) timer 2 underflow signal pwm signal 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 01 16 00 16 03 16 02 16 01 16 00 16 02 16 03 16 (r2l) (r2h) (r2l) (r2h) (r2l) (r2h) pwm period 7.5 clock pwm period 7.5 clock 4 clock 3.5 clock 4 clock 3.5 clock 4 clock note: when the pwm signal ?h? interval expansion function is valid, set ?1? or more to reload register r2h. - cntr pin output valid (w2 3 =1), pwm signal ?h? inter val expansion function invalid (w2 2 =0) - cntr pin output valid (w2 3 =1), pwm signal ?h? interval expansion function valid (w2 2 =1) (note)
rev.1.04 aug 23, 2007 page 39 of 146 rej03b0188-0104 4559 group fig 38. cntr output auto-con trol function by timer 1 timer 1 start cntr output start timer 1 underflow signal pwm signal ? cntr output auto-control circuit operation example 1 (w2 3 = ?1?, w4 1 = ?1?) cntr output * when the cntr1 output auto-control circuit is selected, valid/invalid of cntr output is repeated every timer 1 underflows. ? cntr output auto-control circuit operation example 2 (w2 3 = ?1?) timer 1 start cntr output start timer 1 underflow signal pwm signal register w4 1 timer 1 stop cntr output stop cntr output (1) when the cntr output auto-control function is not selected while the cntr output is invalid, cntr output invalid state is retained. (2) when the cntr output auto-control function is not selected while the cntr output is valid, cntr output valid state is retained. (3) when the timer 1 is stopped, the cntr output auto-control function becomes invalid. (1) (2) (3)
rev.1.04 aug 23, 2007 page 40 of 146 rej03b0188-0104 4559 group fig 39. timer count start/stop timing (r2h) timer 2 underflow signal machine cycle timer 2 count start timing (r2l = ?02 16 ?, r2h = ?02 16 ?, w2 3 = ?1?) register w2 1 mi mi + 1 mi + 2 mi + 3 02 16 00 16 01 16 02 16 00 16 01 16 02 16 (r2l) (r2l) timer 2 count start timing pwm signal timer 2 count value (reload register) timer 2 count source (x in input) (r2h) mi mi + 1 mi + 2 mi + 3 00 16 01 16 02 16 00 16 01 16 02 16 02 16 timer 2 count stop timing (r2l) (r2h) (note 1) tw2a instruction execution (w2 1 1) tw2a instruction execution (w2 1 0) timer 2 underflow signal machine cycle register w2 1 pwm signal timer 2 count value (reload register) timer 2 count source (x in input) timer 2 count stop timing (r2l = ?02 16 ?, r2h = ?02 16 ?, w2 3 = ?1?) notes 1: if the timer count stop timing and the timer underflow timing overlap while the cntr pin output is valid (w2 3 =?1?), a hazard may occur in the pwm signal waveform. 2: when timer count is stopped during ?h? interval of the pwm signal, timer is stopped after the end of the ?h? output interval.
rev.1.04 aug 23, 2007 page 41 of 146 rej03b0188-0104 4559 group watchdog timer watchdog timer provides a method to reset the system when a program run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), wa tchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the inst ruction clocks as the count source from ?ffff 16 ? after system is released from reset. after the count is started, wh en the timer wdt underflow occurs (after the count value of timer wdt reaches ?0000 16 ,? the next count pulse is input), the wdf1 flag is set to ?1.? if the wrst instruction is never executed until the timer wdt underflow occurs (until timer wdt counts 65 534), wdf2 flag is set to ?1,? and the reset pin outputs ?l? level to reset the microcomputer. execute the wrst instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to ?1? after system is released from reset, the watchdog time r function is valid. when the dwdt instruction a nd the wrst instruction are executed continuously, the wef fl ag is cleared to ?0? and the watchdog timer func tion is invalid. the wef flag is set to ?1? at system reset or ram back-up mode. the wrst instruction has the skip function. when the wrst instruction is executed while the wdf1 flag is ?1?, the wdf1 flag is cleared to ?0? and th e next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is ?0?, the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. fig 40. watchdog timer function (1) reset released 65534 count (note) (4) (2) (2) (3) wrst instruction executed (skip occurrence) (5) system reset ffff 16 0000 16 value of 16-bit timer (wdt) wdf1 flag wdf2 flag reset pin output (1) after system is released from reset (= after program is started), timer wdt starts count down. (2) when timer wdt underflow occurs, wdf1 flag is set to ?1.? (3) when the wrst instruction is executed while the wdf1 flag is ?1?, wdf1 flag is cleared to ?0,? the next instruction is skipped. (4) when timer wdt underflow occurs while wdf1 flag is ?1,? wdf2 flag is set to ?1? and the watchdog reset signal is output. (5) the output transistor of reset pin is turned ?on? by the watchdog reset signal and system reset is executed. note: the number of count is equal to the number of ma chine cycle because the count source of watchdog timer is the instruction clock.
rev.1.04 aug 23, 2007 page 42 of 146 rej03b0188-0104 4559 group when the watchdog timer is used, clear the wdf1 flag at the period of 65534 machine cycles or less with the wrst instruction. when the watchdog timer is not used, execute the dwdt instruction and the wrst instruction continuously (refer to figure 41). the watchdog timer is not stopped with only the dwdt instruction. the contents of wdf1 flag and timer wdt are initialized at the power down mode. when using the watchdog timer and the power down mode, initialize the wdf1 flag with th e wrst instruction just before the microcomputer enters the power down mode. also, set the nop instruction after the wrst instruction, for the case when a skip is performed with the wrst instruction (refer to figure 42). fig 41. program example to start/stop watchdog timer fig 42. program example when using the watchdog timer ? ? ? wrst ; wdf1 flag cleared ? ? ? di dwdt ; watchdog timer fu nction enabled/disabled wrst ; wef and wdf1 flags cleared ? ? ? ? ? ? wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof2 ; ram back-up mode oscillation stop ? ? ?
rev.1.04 aug 23, 2007 page 43 of 146 rej03b0188-0104 4559 group lcd function the 4559 group has an lcd (liquid crystal display) controller/ driver. when data are set in lcd ram and timer lc, lcd control registers (l1, l2, l3, c1, c2, c3), and timer control registers (w3, w4), the lcd controller/driver automatically reads the display data and controls the lcd display by setting duty and bias. 4 common signal output pins and 32 segment signal output pins can be used to drive the lcd. by using these pins, up to 128 pixels (when internal power, 1/4 duty and 1/3 bias are selected) can be controlled to display. when using the external input, set necessary pins with the lcd co ntrol register 2 and apply the proper voltage to the pins . the lcd power input pins (v lc3 ?v lc1 ) are also used as pins seg 0 ?seg 2 . when seg 0 is selected, the internal power (v dd ) is used for the lcd power. (1) duty and bias there are 3 combinations of duty and bias for displaying data on the lcd. use bits 0 and 1 of lcd control register (l1) to select the proper display method for the lcd panel being used. ? 1/2 duty, 1/2 bias ? 1/3 duty, 1/3 bias ? 1/4 duty, 1/3 bias table 18 table 11 duty and maximum number of displayed pixels note. leave unused com pins open . fig 43. lcd controller/driver duty maximum number of displayed pixels used com pins 1/2 64 pixels com 0 , com 1 (note) 1/3 96 pixels com 0? com 2 (note) 1/4 128 pixels com 0? com 3 common driver bias control segment driver segment driver segment driver segment driver segment driver segment driver selector lcd ram register a selector selector selector selector selector l1 2 l2 0 l2 3 v dd l2 3 l2 2 l2 1 l1 3 l1 3 l1 3 l1 1 l1 0 decoder lcd on/off control 1/2, 1/3, 1/4 counter lcd clock (from timer lc) com 3 com 2 com 1 com 0 seg 0 /v lc3 seg 1 /v lc2 seg 2 /v lc1 seg 3 .... .... .... .... .... .... .... .... .... .... p0 0 /seg 16 c1 0 to c1 3 l2 3 l2 2 l2 1 c2 0 to c2 3 l3 0 to l3 3 c3 0 to c3 3 p0 3 /seg 19 p1 0 /seg 20 p1 3 /seg 23 p2 0 /seg 24 p2 3 /seg 27 p3 0 /seg 28 p3 3 /seg 31 seg 15 r r .... .... .... .... r r r r to to to to to
rev.1.04 aug 23, 2007 page 44 of 146 rej03b0188-0104 4559 group (2) lcd clock control the lcd clock is determined by the timer lc setting value and timer lc count source. after setting data to timer lc, timer lc st arts counting by setting count source with bit 2 of regist er w4 and setting bit 3 of register w4 to ?1.? accordingly, the frequency (f) of the lcd clock is obtained by the following formula. number s ((1) to (3)) shown below the formula correspond to numbers in figure 44, respectively. ? when using the system cloc k (stck) as timer lc count source (w4 2 =?1?) f = stck (1) (2) (3) [lc: 0 to 15] ? when using the bit 4 of timer 3 as timer lc count source (w4 2 =?0?) f = t3 4 (1) (2) (3) [lc: 0 to 15] the frame frequency and frame pe riod for each display method can be obtained by the following formula: frame frequency = (hz) frame frequency = (hz) f: lcd clock frequency 1/n: duty fig 44. lcd clock control circuit structure (3) lcd ram ram contains areas corresponding to the liquid crystal display. when ?1? is written to this lcd ram, the display pixel corresponding to the bit is automatically displayed. fig 45. lcd ram map timer lc (4) reload register rlc (4) (tlca) register a 1/2 lcd clock (tlca) w4 2 0 1 w4 3 t3 4 stck (3) (1) (2) z x 1 8 9 10 11 12 13 14 15 com y bit 0 seg 0 seg 1 0 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 0 seg 0 seg 1 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 1 seg 0 seg 1 2 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 2 seg 0 seg 1 3 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 com 3 1 seg 8 seg 9 0 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 0 seg 8 seg 9 1 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 1 seg 8 seg 9 2 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 2 seg 8 seg 9 3 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 com 3 2 seg 16 seg 17 0 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 0 seg 16 seg 17 1 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 1 seg 16 seg 17 2 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 2 seg 16 seg 17 3 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 3 seg 24 seg 25 0 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 com 0 seg 24 seg 25 1 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 com 1 seg 24 seg 25 2 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 com 2 seg 24 seg 25 3 seg 26 seg 27 seg 28 seg 29 seg 30 seg 31 com 3 lc + 1 1 2 1 lc + 1 1 2 1 n f f n
rev.1.04 aug 23, 2007 page 45 of 146 rej03b0188-0104 4559 group (4) lcd drive waveform when ?1? is written to a bit in the lcd ram data, the voltage difference between common pin and segment pin which correspond to the bit au tomatically becomes lv lc3 l and the display pixel at the cross section turns on. when returning from reset, and in the ram back-up mode, a display pixel turns off becaus e every segment output pin and common output pin becomes v lc3 level. fig 46. lcd controller/driver structure 1/2 duty, 1/2 bias: when writing (xx10) 2 to address m (1, 2, 8) in ram. v lc3 v ss v lc1 =v lc2 v lc3 v ss v lc1 =v lc2 (2/f) 1 flame (3/f) (4/f) on off voltage level v lc3 v lc2 v ss v lc1 v lc3 v lc2 v ss v lc1 voltage level v lc3 v lc2 v ss v lc1 v lc3 v lc2 v ss v lc1 voltage level com 0 com 0 com 0 com 1 com 1 com 2 com 2 com 3 com 1 com 1 com 2 com 3 com 2 com 1 com 0 com 1 com 0 com 0 com 1 seg 16 seg 16 seg 16 seg 16 seg 16 com 2 seg 16 com 3 seg 16 com 2 seg 16 com 1 seg 16 com 0 seg 16 com 1 seg 16 com 0 seg 16 com 0 seg 16 seg 16 seg 16 0 1 x x m (1, 2, 8) (bit 0) m (1, 2, 8) (bit 0) m (1, 2, 8) (bit 0) (bit 3) (bit 3) (bit 3) on off on 1 0 1 x on off on off 0 1 0 1 f : lcd clock frequency x: set an arbitrary value. (these bits are not related to set the drive waveform at each duty.) 1/f 1/f 1/f 1/3 duty, 1/3 bias: when writing (x101) 2 to address m (1, 2, 8) in ram. 1/4 duty, 1/3 bias: when writing (1010) 2 to address m (1, 2, 8) in ram. 1 flame 1 flame
rev.1.04 aug 23, 2007 page 46 of 146 rej03b0188-0104 4559 group (5) lcd power supply circuit select the lcd power supply circ uit suitable for the using lcd panel. the lcd power supply circuit is fixed by the followings; ? the internal dividing resistor is controlled by bit 0 of register l2. ? the internal dividing resistor is selected by bit 3 of register l1. ? the bias condition is selected by bits 0 a nd 1 of register l1. ? internal dividing resistor the 4553 group has the internal dividing resistor for lcd power supply. when bit 0 of register l2 is se t to 0?, the internal dividing resistor is valid. however, when the lcd is turned off by setting bit 2 of register l1 to 0?, the internal dividing resistor is turned off. the same six resistor (r) is prep ared for the internal dividing resistor. according to the setting value of bit 3 of register l1 and using bias condition, the resistor is prepared as follows; ?l1 3 = ?0?, 1/3 bias used: 2r 3 = 6r ?l1 3 = ?0?, 1/2 bias used: 2r 2 = 4r ?l1 3 = ?1?, 1/3 bias used: r 3 = 3r ?l1 3 = ?1?, 1/2 bias used: r 2 = 2r ?seg 0 /v lc3 pin the selection of seg 0 /v lc3 pin function is controlled with the bit 3 of register l2. when the v lc3 pin function is select ed, apply voltage of v lc3 < v dd to the pin externally. when the seg 0 pin function is selected, v lc3 is connected to v dd internally. ? seg 1 /v lc2 , seg 2 /v lc1 pin the selection of seg 1 /v lc2 pin function is controlled with the bit 2 of register l2. the selection of seg 2 /v lc1 pin function is controlled with the bit 1 of register l2. when the v lc2 pin and v lc1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0 < v lc1 < v lc2 < v lc3 to these pins. short the v lc2 pin and v lc1 pin at 1/2 bias. when the v lc2 pin and v lc1 pin functions are selected and the internal dividing resistor is used, the dividing voltage value generated internally is output from the v lc1 pin and v lc2 pin. the v lc2 pin and v lc1 pin have the same electric potential at 1/2 bias. when seg1 and seg2 pin func tions are selected, use the internal dividing resistor (l2 0 = ?0?). in this time, v lc2 and v lc1 are connected to the generated dividing voltage. fig 47. lcd power supply circuit example (1/3 bias condition selected) v ss v lc3 v lc2 v lc1 v lc3 seg 1 seg 2 (b) register l2 = (1000) 2 v ss v lc3 v lc2 v lc1 seg 1 seg 2 (a) register l2 = (0000) 2 v ss v lc3 v lc2 v lc1 v lc3 (d) register l2 = (1111) 2 v ss v lc3 v lc2 v lc1 v lc3 (c) register l2 = (1110) 2 external power supply seg 0 v lc2 v lc1 v lc2 v lc1 external power supply external power supply
rev.1.04 aug 23, 2007 page 47 of 146 rej03b0188-0104 4559 group (6) lcd control register ? lcd control register l1 register l1 controls duty/bias selection, lcd operation, internal dividing resistor selection. set the contents of this register through register a with the tl1a instruction. the tal1 instruction can be used to transf er the contents of register l1. ? lcd control register l2 register l2 controls internal dividing resistor operation, selection of pin functions; seg 0 /v lc3 , seg 1 /v lc2 , seg 2 /v lc1 . set the contents of this register through register a with the tl2a instruction. ? lcd control register l3 register l3 controls selection of pin functions; p2 0 /seg 24 to p2 3 /seg 27 . set the contents of this register through register a with the tl3a instruction. ? lcd control register c1 register c1 controls selection of pin functions; p0 0 /seg 16 to p0 3 /seg 19 . set the contents of this register through register a with the tc1a instruction. ? lcd control register c2 register c2 controls selection of pin functions; p1 0 /seg 20 to p1 3 /seg 23 . set the contents of this register through register a with the tc2a instruction. ? lcd control register c3 register c3 controls selection of pin functions; p3 0 /seg 28 to p3 3 /seg 31 . the contents of this register through register a with the tc3a instruction. note 1.?r? represents read enabled, and ?w? represents write enabled. note 2.?r (resistor) multiplied by 3? is used at 1/ 3 bias, and ?r multiplied by 2? is used at 1/2 bias. note 3.v lc3 is connected to v dd internally when seg 0 pin is selected. note 4.use internal di viding resistor when seg 1 and seg 2 pins are selected. table 19 lcd control registers (1) lcd control register l1 at reset : 0000 2 at power down : state retained r/w tal1/tl1a l1 3 internal dividing re sistor for lcd power supply selection bit (note 2) 0 2r 3, 2r 2 1 r 3, r 2 l1 2 lcd control bit 0stop (off) 1 operating lcd duty and bias selection bits l1 1 l1 duty bias l1 1 0 0 not available not available 011/2 1/2 101/3 1/3 l1 0 111/4 1/3 lcd control register l2 at reset : 0000 2 at power down : state retained w tl2a l2 3 seg 0 /v lc3 pin function switch bit (note 3) 0 seg 0 1v lc3 l2 2 seg 1 /v lc2 pin function switch bit (note 4) 0 seg 1 1v lc2 l2 1 seg 2 /v lc1 pin function switch bit (note 4) 0 seg 2 1v lc1 l2 0 internal dividing resistor for lcd power supply control bit 0 internal dividing resistor valid 1 internal dividing resistor invalid lcd control register l3 at reset : 1111 2 at power down : state retained w tl3a l3 3 p2 3 /seg 27 pin function switch bit 0 seg 27 1p2 3 l3 2 p2 2 /seg 26 pin function switch bit 0 seg 26 1p2 2 l3 1 p2 1 /seg 25 pin function switch bit 0 seg 25 1p2 1 l3 0 p2 0 /seg 24 pin function switch bit 0 seg 24 1p2 0
rev.1.04 aug 23, 2007 page 48 of 146 rej03b0188-0104 4559 group table 20 lcd control registers (2) note 1.?r? represents read enabled, and ?w? represents write enabled. lcd control register c1 at reset : 1111 2 at power down : state retained w tc1a c1 3 p0 3 /seg 19 pin function switch bit 0 seg 19 1p0 3 c1 2 p0 2 /seg 18 pin function switch bit 0 seg 18 1p0 2 c1 1 p0 1 /seg 17 pin function switch bit 0 seg 17 1p0 1 c1 0 p0 0 /seg 16 pin function switch bit 0 seg 16 1p0 0 lcd control register c2 at reset : 1111 2 at power down : state retained w tc2a c2 3 p1 3 /seg 23 pin function switch bit 0 seg 23 1p1 3 c2 2 p1 2 /seg 22 pin function switch bit 0 seg 22 1p1 2 c2 1 p1 1 /seg 21 pin function switch bit 0 seg 21 1p1 1 c2 0 p1 0 /seg 20 pin function switch bit 0 seg 20 1p0 0 lcd control register c3 at reset : 1111 2 at power down : state retained w tc3a c3 3 p3 3 /seg 31 pin function switch bit 0 seg 31 1p3 3 c3 2 p3 2 /seg 30 pin function switch bit 0 seg 30 1p3 2 c3 1 p3 1 /seg 29 pin function switch bit 0 seg 29 1p3 1 c3 0 p3 0 /seg 28 pin function switch bit 0 seg 28 1p3 0
rev.1.04 aug 23, 2007 page 49 of 146 rej03b0188-0104 4559 group reset function system reset is performed by the followings: ? ?l? level is applied to the reset pin externally, ? system reset instruction (srst) is executed, ? reset occurs by watchdog timer, ? reset occurs by built-in power-on reset ? reset occurs by voltage drop detection circuit then when ?h? level is applied to reset pin, software starts from address 0 in page 0. (1) reset pin input system reset is performed ce rtainly by applying ?l? level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended opera ting conditions. fig 48. structure of reset pin and its peripherals fig 49. reset pin input waveform and reset release timing power-on reset circuit wef voltage drop detection circuit reset pin (note 2) (note 1) (note 1) pull-up transistor internal reset signal watchdog reset signal srst instruction notes 1: this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less. 0.3v dd 0.85v dd (note 1) program starts (address 0 in page 0) reset input 1 machine cycle or more reset f(ring) notes 1: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. 2: it depends on the internal state at reset. on-chip oscillator (internal oscillator) is counted 1376 times (note 2). =
rev.1.04 aug 23, 2007 page 50 of 146 rej03b0188-0104 4559 group (2) power-on reset reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 v to the minimum voltage of recommended operating conditions to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply voltage reaches the minimum operating voltage. (3) system reset instruction (srst) by executing the srst instructi on, ?l? level is output to reset pin and system reset is performed. fig 50. power-on reset operation note 1. output latch is set to ?1.? note 2. the output structure is n-channel open-drain. note 3. pull-up transistor is turned off. 100 s or less v dd (note) power-on reset circuit output internal reset signal note: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. reset released reset state power-on table 21 port state at reset name function state d 0 ? d 4 d 0 ? d 4 high-impedance (notes 1, 2) d 5 /int d 5 high-impedance (notes 1, 2) x cin /d 6 , x cout /d 7 x cin , x cout sub-clock input p0 0 /seg 16 ? p0 3 /seg 19 p0 0 ? p0 3 high-impedance (notes 1, 2, 3) p1 0 /seg 20 ? p1 3 /seg 23 p1 0 ? p1 3 high-impedance (notes 1, 2, 3) p2 0 /seg 24 ? p2 3 /seg 27 p2 0 ? p2 3 high-impedance (notes 1, 2, 3) p3 0 /seg 28 ? p3 3 /seg 31 p3 0 ? p3 3 high-impedance (notes 1, 2, 3) seg 0 /v lc3 ? seg 2 /v lc1 seg 0 ? seg 2 v lc3 (v dd ) level seg 3 ? seg 15 seg 3 ? seg 15 v lc3 (v dd ) level com 0 ? com 3 com 0 ? com 3 v lc3 (v dd ) level c/cntr c/cntr ?l? (v ss ) level
rev.1.04 aug 23, 2007 page 51 of 146 rej03b0188-0104 4559 group (4) internal state at reset figure 51 and 52 shows internal state at reset (they are the same after system is released from reset). the contents of timers, registers, flags and ram excep t shown in figure 51 and 52 are undefined, so set the initial value to them. fig 51. internal state at reset (1) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? program counter (pc) address 0 in page 0 is set to program counter. ? interrupt enable flag (inte) ? power down flag (p) ? external 0 interrupt request flag (exf0) ? interrupt control register v1 ? interrupt control register v2 ? interrupt control register i1 ? timer 1 interrupt request flag (t1f) ? timer 2 interrupt request flag (t2f) ? timer 3 interrupt request flag (t3f) ? watchdog timer flags (wdf1, wdf2) ? watchdog timer enable flag (wef) ? timer control register pa ? timer control register w1 ? timer control register w2 ?timer control register w3 ? timer control register w4 ? clock control register mr ? clock control register rg ? lcd control register l1 ? lcd control register l2 ? lcd control register l3 ? lcd control register c1 ? lcd control register c2 ? lcd control register c3 0 (interrupt disabled) 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0 0 0 0 0 0 0 0 0 0 1 0 (prescaler stopped) 0 (timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 (timer 3 stopped) (timer lc stopped) 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
rev.1.04 aug 23, 2007 page 52 of 146 rej03b0188-0104 4559 group fig 52. internal state at reset (2) ? key-on wakeup control register k0 ? key-on wakeup control register k1 ? key-on wakeup control register k2 ? key-on wakeup control register k3 ? pull-up control register pu0 ? pull-up control register pu1 ? pull-up control register pu2 ? pull-up control register pu3 ? port output structure control register fr0 ? port output structure control register fr1 ? port output structure control register fr2 ? port output structure control register fr3 ? high-order bit reference enable flag (uptf) ? carry flag (cy) ? register a ? register b ? register d ? register e ? register x ? register y ? register z ? stack pointer (sp) ? operation source clock ? ceramic resonator circuit ? rc oscillation circuit ? quartz-crystal oscillator 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 ?x? represents undefined. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 on-chip oscillator (oeprating) oeprating stop oeprating 0 0 0 0
rev.1.04 aug 23, 2007 page 53 of 146 rej03b0188-0104 4559 group voltage drop detection circuit (with skip judgment) the built-in voltage drop detectio n circuit is used to set the voltage drop detection circuit flag (vdf) or to perform system reset. fig 53. voltage drop detection reset circuit (1) operating state of voltage drop detection circuit the voltage drop detection circ uit becomes valid by inputting ?h? to the vdce pin and it beco mes invalid by inputting ?l.? when not executing the svde in struction under ?h? level of the vdce pin, the voltage drop detection circui t become invalid in power down state (ram back-up, clock operating mode). as for this, the voltage drop detection ci rcuit becomes valid at returning from power down, again. when executing the svde instru ction under ?h? level of the vdce pin, the voltage drop de tection circuit becomes valid in power down state (ram back -up, clock ope rating mode). the state of executing svde instruction can be cleared by system reset. note. ?o? indicates valid, ?? indicates invalid. (note 1) (note 1) vdce (note 2) v rst - /v rst + ? + voltage drop detection circuit v skip ? + flag occurrence reset occurrence vdf v dd v dd voltage drop detection circuit reset signal s r q s r q svde instruction internal reset signal epof instruction + pof instruction epof instruction + pof2 instruction key-on wakeup signal internal reset signal voltage drop detection circuit flag skip judgement (snzvd instruction) notes 1: this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less. timer 3 underflow signal table 22 operating state of voltage drop detection circuit vdce pin svde instruction at cpu operating at power down ?l? no execute execute ?h? no execute o execute o o
rev.1.04 aug 23, 2007 page 54 of 146 rej03b0188-0104 4559 group (2) voltage drop detection circuit flag (vdf) voltage drop detection circuit flag (vdf) is set to ?1? when the supply voltage goes the skip occurrence voltage (v skip ) or less. moreover, voltage drop detection circuit flag (vdf) is cleared to ?0? when the supply voltage go es the skip occurrence voltage (v skip ) or more. the state of the voltage drop detection circuit flag (vdf) can be examined with the skip instruction (snzvd). even when the skip instructio n is executed, the voltage drop detection circuit flag is not cleared to ?0?. refer to the electrical characteristics for skip occurrence voltage value. (3) voltage drop detection circuit reset system reset is performed when the supply voltage goes the reset occurrence voltage (v rst - ) or less. when the supply voltage goes reset releas e voltage (v rst + ) or more, the oscillation circuit goes to be in the operating enabled state and system reset is released . refer to the electrical characte ristics for reset occurrence value and reset release voltage value. fig 54. voltage drop detection circuit operation waveform fig 55. v dd and v rst - (4) note on voltage drop detection circuit the voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recommende d operating conditions. when the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up, depending on the capacity value of the bypass capacitor added to the power s upply pin, the following case may cause program failure (figure 55); supply voltage does not fall below to v rst - , and its voltage re- goes up with no reset. in such a case, please design a system which supply voltage is once reduced below to v rst - and re-goes up after that. v dd voltage drop detection circuit flag (vdf) v rst + (reset release voltage) v rst - (reset occurrence voltage) voltage drop detection circuit reset signal note 1: microcomputer starts operation after on-chip oscillator clock is counted 1376 times. (note 1) v skip (skip occurrence voltage) v dd v rst + v rst - v dd v rst + v rst - recommended operating condition min.value normal operation reset no reset program failure may occur. recommended operating condition min.value
rev.1.04 aug 23, 2007 page 55 of 146 rej03b0188-0104 4559 group power down function the 4559 group has 2-type power down functions. system enters into each power down state by executing the following instructions. ? clock operating mode ................. epof and pof instructions ? ram back-up mode ................... epof and pof2 instructions when the epof instru ction is not executed before the pof or pof2 instruction is executed, thes e instructions ar e equivalent to the nop instruction. (1) clock operating mode the following functions and states are retained. ?ram ? reset circuit ?x cin ?x cout oscillation ?lcd display ?timer 3 (2) ram back-up mode the following functions and states are retained. ?ram ? reset circuit (3) warm start condition the system returns from the power down state when; ? external wakeup signal is input ? timer 3 underflow occurs in the power down mode. in either case, the cpu starts executing the software from address 0 in page 0. in this case, the p flag is ?1.? (4) cold start condition the cpu starts executing the softwa re from address 0 in page 0 when; ? external ?l? level is input to reset pin, ? execute system reset instruction (srst instruction) ? reset by watchdog timer is performed ? reset by internal power-on reset, or ? reset by the voltage drop dete ction circuit is performed. in this case, the p flag is ?0.? (5) identification of the start condition warm start or cold start can be identified by examining the state of the power down flag (p) with the snzp instruction. the warm start condition from the clock operating mode can be identified by examining the state of t3f flag. note 1. ?o? represents that the function can be retained, and ? ? represents that the function is initialized. registers and flags other than the above are undefined at power down mode, and set an initial value after returning. note 2. the stack pointer (sp) points the level of the stack register and is initialized to ?7? at power down mode. note 3. the state of the timer is undefined. note 4. initialize the wdf1 flag with the wrst instruction, and then go into the power down state. note 5. lcd is turned off. note 6. when the svde instruction is executed, this function is valid at power down. note 7. in the power down mode, c/cntr pin outputs ?l? level. however, when the cntr input is selected (w1 1 , w1 0 =?11?), c/cntr pin is in an input enabled state (output = high-impedance). other ports retain their respective output levels. table 23 functions and states retained at power down mode function power down mode clock operating ram back-up program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram o o interrupt control registers v1, v2 interrupt control registers i1 o o selected oscillation circuit o o clock control register mr, rg o o timer 1, timer 2 functions (note 3) (note 3) timer 3 function o (note 3) timer lc function o (note 3) watchdog timer function (note 4) (note 4) timer control registers pa, wa timer control registers w1, w3, w4 o o lcd display function o (note 5) lcd control registers l1 to l3, c1 to c3 oo voltage drop detection circuit (note 6) (note 6) port level (note 7) (note 7) key-on wakeup control registers k0 to k2 oo pull-up control registers pu0, pu1 o o port output structure control registers fr0 to fr2 oo external interrupt request flags (exf0) timer interrupt request flags (t1f, t2f) (note 3) (note 3) timer interrupt request flag (t3f) o (note 3) interrupt enable flag (inte) voltage drop detection circuit flag (vdf) watchdog timer flags (wdf1, wdf2) (note 4) (note 4) watchdog timer enable flag (wef) (note 4) (note 4)
rev.1.04 aug 23, 2007 page 56 of 146 rej03b0188-0104 4559 group (6) return signal an external wakeup signal or timer 3 interrupt request flag (t3f) is used to return from the clock operating mode. an external wakeup signal is used to return from the ram back- up mode because the oscillation is stopped. table 24 shows the return condition for each return source. (7) control registers ? key-on wakeup control register k0 register k0 controls the por ts p0 and p1 key-on wakeup function. set the contents of th is register through register a with the tk0a instruction. in addition, the tak0 instruction can be used to transfer the conten ts of register k0 to register a. ? key-on wakeup control register k1 register k1 controls the return condition and the selection of valid waveform/level of port p1. set the contents of this register through register a with the tk1a instruction. in addition, the tak1 instruction can be used to transfer the contents of register k0 to register a. ? key-on wakeup control register k2 register k2 controls the port p3 and int pin key-on wakeup function and the selection of retu rn condition of int pin. set the contents of this register through register a with the tk2a instruction. in addition, the t ak2 instruction can be used to transfer the contents of register k2 to register a. ? key-on wakeup control register k3 register k3 controls the selec tion of return condition and valid waveform/level of port p3. set the contents of this register through register a with the tk3a instruction. in addition, the tak3 instruction can be used to transfer the contents of register k3 to register a. ? pull-up control register pu0 register pu0 controls the on/off of the port p0 pull-up transistor. set the contents of th is register through register a with the tpu0a instruction. in addition, the tapu0 instruction can be used to transfer the contents of register pu0 to register a. ? pull-up control register pu1 register pu1 controls the on/off of the port p1 pull-up transistor. set the contents of th is register through register a with the tpu1a instruction. in addition, the tapu1 instruction can be used to transfer the contents of register pu1 to register a. ? pull-up control register pu2 register pu2 controls the on/ off of the ports p2 pull-up transistor. set the contents of th is register through register a with the tpu2a instruction. in addition, the tapu2 instruction can be used to transfer the contents of register pu2 to register a. ? pull-up control register pu3 register pu3 controls the on/ off of the ports p3 pull-up transistor. set the contents of th is register through register a with the tpu3a instruction. in addition, the tapu3 instruction can be used to transfer the contents of register pu3 to register a. ? external interrupt control register i1 register i1 controls the input control and the selection of valid waveform/level of int pin. set the contents of this register through register a with the ti1a instruction. in addition, the tai1 instruction can be used to transfer the contents of register i1 to register a. table 24 return source and return condition return source return condition remarks external wakeup signal ports p0 0 ? p0 3 ports p1 0 ? p1 3 ports p2 0 ? p2 3 return by an external falling edge (?h? ?l?). for ports p0 and p1, the key-on wakeup function can be selected by two port unit, for port p2, it can be selected by a unit. ports p3 0 ? p3 3 return by an external ?h? level or ?l? level input, or rising edge (?l? ?h?) or falling edge (?h? ?l?). return by an external ?l? level input, the key-on wakeup function can be selected by two port unit. select the return level (?l? level or ?h? level) and return condition (return by level or edge) with register k3 according to the external state before going into the power down state. int pin return by an external ?h? level or ?l? level input, or rising edge (?l? ?h?) or falling edge (?h? ?l?). when the return level is input, the interrupt request flag (exf0) is not set. select the return level (?l? level or ?h? level) with register i1 and return condition (return by level or edge) with register k2 according to the external state before going into the power down state. timer 3 interrupt request flag (t3f) return by timer 3 underflow or by setting t3f to ?1?. it can be used in the clock operating mode. clear t3f with the snzt3 instruction before system enters into the power down state. when system enters into the power down state while t3f is ?1?, system returns from the state immediately because it is recognized as return condition.
rev.1.04 aug 23, 2007 page 57 of 146 rej03b0188-0104 4559 group fig 56. state transition fig 57. set source and clear source of the p flag fig 58. start condition identified example using the snzp instruction b e clock operating mode f(ring): stop f(x in ): stop f(x cin ): operating key-on wakeup (stabilizing time c ) execution d ram back-up mode high-speed mode d operation source clock: f(x cin ) mr 1 ,mr 0 00 mr 1 ,mr 0 10 low-speed mode execution key-on wakeup (stabilizing time e ) execution (stabilizing time e ) (stabilizing time c ) crck instruction no execution stabilizing time a : microcomputer starts its operation after counting the f(ring) to 1376 times. stabilizing time b : microcomputer starts its operation after counting the f(ring) to (system clock division ratio x 171) times. stabilizing time c : microcomputer starts its operation after counting the f(x in ) to (system clock division ratio x 171) times. stabilizing time d : microcomputer starts its operation after counting the f(x in ) to (system clock division ratio x 171) times. stabilizing time e : microcomputer starts its operation after counting the f(x cin ) to (system clock division ratio x 171) times. reset a execution key-on wakeup (stabilizing time b ) execution (stabilizing time b ) (stabilizing time a ) operation state operation source clock: f(ring) c execution key-on wakeup (stabilizing time d ) execution (stabilizing time d ) f(ring): stop f(x in ): stop f(x cin ): stop crck instruction execution mr 1 ,mr 0 00 mr 1 ,mr 0 01 internal mode mr 1 ,mr 0 10 mr 1 ,mr 0 01 notes epof + pof instruction epof + pof instruction epof + pof instruction epof + pof instruction key-on wakeup timer 3 underflow key-on wakeup timer 3 underflow key-on wakeup timer 3 underflow key-on wakeup timer 3 underflow epof + pof 2 instruction epof + pof 2 instruction epof + pof 2 instruction epof + pof 2 instruction execution ? ? ? ? ? ? 1: selection of the system clock by the clock control registers mr and rg is state retained at power down. the waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers mr and rg before transition to the power down state. and generate the wait time until the oscillatio n is stabilized, and then, switch the system clock. 6: when the unoperating clock is selected as the system clock, turn it on by the clock control register rg, if the crck instruction is not executed, the ceramic resonator is selected as the main clock f(x in ). 5: when the rc oscillation circuit is used, executing the crck instruction is required. ?mainclock(f(x in )) and sub-clock (f(x cin )) are valid. ? a ceramic resonator is selected as the main clock (f(x in )). 4: the state after system is released from reset; 3: continuous execution of the epof instruction and the pof2 instruction is required to go into the ram back-up state. 2: continuous execution of the epof instruction and the pof instruction is required to go into the clock operating state. ceramic resonator rc oscillation operation state operation source clock: f(x in ) operation state operation source clock: f(x in ) on-chip oscillator operation state quartz-crystal oscillation 7: the sub-clock (quartz-crystal oscillation) is operating except in state d. s r q powerdownflagp pof or pof2 instruction reset input set source clear source system reset ??????? ?????? epof instruction + pof or pof2 instruction epof instruction + p program start p= ?1? ? warm start cold start no t3f = ? return from timer 3 underflow return from external wakeup signal ?1? yes yes no snzt3 instruction snzp instruction
rev.1.04 aug 23, 2007 page 58 of 146 rej03b0188-0104 4559 group note 1. ?r? represents read enabled, and ?w? represents write enabled. note 2. to be invalid (k2 2 = ?0?) key-on wakeup of ports p3 0 and p3 1 , set the registers k3 0 and k3 1 to ?0.? note 3. to be invalid (k2 3 = ?0?) key-on wakeup of ports p3 2 and p3 3 , set the registers k3 2 and k3 3 to ?0.? table 25 key-on wakeup control register key-on wakeup control register k0 at reset : 0000 2 at power down : state retained r/w tak0/tk0a k0 3 ports p1 2 , p1 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 2 ports p1 0 , p1 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 1 ports p0 2 , p0 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 0 ports p0 0 , p0 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k1 at reset : 0000 2 at power down : state retained r/w tak1/tk1a k1 3 port p2 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 2 port p2 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 1 port p2 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 0 port p2 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k2 at reset : 0000 2 at power down : state retained r/w tak2/tk2a k2 3 ports p3 2 , p3 3 key-on wakeup control bit (note 3) 0 key-on wakeup not used 1 key-on wakeup used k2 2 ports p3 0 , p3 1 key-on wakeup control bit (note 2) 0 key-on wakeup not used 1 key-on wakeup used k2 1 int pin return condition selection bit 0 return by level 1 return by edge k2 0 int pin key-on wakeup control bit 0 key-on wakeup invalid 1 key-on wakeup valid key-on wakeup control register k3 at reset : 0000 2 at power down : state retained r/w tak3/tk3a k3 3 ports p3 2 , p3 3 return condition selection bit (note 3) 0 return by level 1 return by edge k3 2 ports p3 2 , p3 3 valid waveform/level selection bit (note 3) 0 falling waveform/?l? level 1 rising waveform/?h? level k3 1 ports p3 0 , p3 1 return condition selection bit (note 2) 0 return by level 1 return by edge k3 0 ports p3 0 , p3 1 valid waveform/level selection bit (note 2) 0 falling waveform/?l? level 1 rising waveform/?h? level
rev.1.04 aug 23, 2007 page 59 of 146 rej03b0188-0104 4559 group note 1.?r? represents read enabled, and ?w? represents write enabled. table 26 pull-up control register pull-up control register pu0 at reset : 0000 2 at power down : state retained r/w tapu0/tpu0a pu0 3 port p0 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 2 port p0 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 1 port p0 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 0 port p0 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu1 at reset : 0000 2 at power down : state retained r/w tapu1/tpu1a pu1 3 port p1 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 2 port p1 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 1 port p1 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 0 port p1 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu2 at reset : 0000 2 at power down : state retained r/w tapu2/tpu2a pu2 3 port p2 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 2 port p2 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 1 port p2 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 0 port p2 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu3 at reset : 0000 2 at power down : state retained r/w tapu3/tpu3a pu3 3 port p3 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 2 port p3 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 1 port p3 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 0 port p3 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on
rev.1.04 aug 23, 2007 page 60 of 146 rej03b0188-0104 4559 group table 27 interrupt control register note 1. ?r? represents read enabled, and ?w? represents write enabled. note 2. when the contents of i1 2 and i1 3 are changed, the external interrupt request flag exf0 may be set. interrupt control register i1 at reset : 0000 2 at power down : state retained r/w tai1/ti1a i1 3 int pin input control bit (note 2) 0 int pin input disabled 1 int pin input enabled i1 2 interrupt valid waveform for int pin/ return level selection bit (note 2) 0 falling waveform (?l? level of int pi n is recognized with the snzi0 instruction)/?l? level 1 rising waveform (?h? level of int pin is recognized with the snzi0 instruction)/?h? level i1 1 int pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i1 0 int pin timer 1 count start synchronous circuit selection bit 0 timer 1 count start synchronous circuit not selected 1 timer 1 count start synchronous circuit selected
rev.1.04 aug 23, 2007 page 61 of 146 rej03b0188-0104 4559 group clock control the clock control circuit consis ts of the foll owing circuits. ? on-chip oscillator (internal oscillator) ? ceramic resonator ? rc oscillation circuit ? quartz-crystal os cillation circuit ? multi-plexer (clock selection circuit) ? frequency divider ? internal clock generating circuit the system clock and the instruct ion clock are generated as the source clock for opera tion by these circuits. figure 59 shows the structure of the clock control circuit. the 4559 group operates by the on-chip oscillator clock (f(ring)) which is the internal osc illator after system is released from reset. also, the ceramic resonator or th e rc oscillation can be used for the main clock (f(x in )) of the 4559 group. the quartz-crystal oscillator can be used for sub-clock (f(x cin )). fig 59. clock control circuit structure mr 3, mr 2 00 01 10 11 q s r q r timer 3 underflow signal epof instruction + x cout x cin r epof instruction + 10 mr 1 ,mr 0 11 system clock (stck) instruction clock (instck) multi- plexer quartz-crystal oscillation on-chip oscillator (internal oscillator) x out x in ceramic resonance rc oscillation internal clock generating circuit (divided by 3) rg 1 01 rg 0 rg 2 divided by 2 divided by 4 divided by 8 division circuit s qs crck instruction internal reset signal key-on wakeup signal pof instruction pof2 instruction
rev.1.04 aug 23, 2007 page 62 of 146 rej03b0188-0104 4559 group (1) on-chip oscillator operation after system is released from reset, the mcu starts operation by the clock output from the on-chip oscillator which is the internal oscillator. the clock frequency of the on-chip oscillator depends on the supply voltage and the ope ration temperature range. be careful that variable frequencies when designing application products. (2) main clock generating circuit (f(x in )) when the mcu operates by the ceramic resonator or the rc oscillator as the main clock (f(x in )). after system is released from reset, the ceramic oscillation is valid for main clock. the ceramic oscillation is invalid and the rc oscillation circuit is valid with the crck instruction. the crck instruction can be executed only once. execute the crck instruction in the initial setting routine (executing it in address 0 in page 0 is recommended). when the main clock (f(x in )) is not used, connect x in pin to v ss and leave x out pin open, and do not execute the crck instruction (figure 61). (3) ceramic resonator when the ceramic resonator is used as the main clock (f(x in )), connect the ceramic res onator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in between pins x in and x out (figure 62). do not execute the crck instruction in program. (4) rc oscillation when the rc oscillation is used as the main clock (f(x in )), connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 63). to select rc oscillation as the system clock, select the main clock (f(x in ) as the system clock by bits 0 and 1 of the clock control register mr. the frequency is affected by a capacitor, a resistor and a microcomputer. so, set the cons tants within the range of the frequency limits. fig 60. switch to ceramic resonance/rc oscillation fig 61. handling of x in and x out when operating on- chip oscillator fig 62. ceramic resonator external circuit fig 63. external rc oscillation circuit reset crck ? ceramic resonator circuit valid ? rc oscillation circuit invalid main clock (f(x in )) ? ceramic resonator circuit invalid ? rc oscillation circuit valid * do not use the crck instruction in program. 4559 x in x out 4559 x in x out rd c in c out do not execute the crck instruction in program. * note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manufacturer?s recommended value because constants such as capacitance depend on the resonator. 4559 x in x out r c * execute the crck instruction in program.
rev.1.04 aug 23, 2007 page 63 of 146 rej03b0188-0104 4559 group (5) external clock when the external clock signal is used as the main clock (f(x in )), connect the x in pin to the clock source and leave x out pin open (figure 64). do not execute the crck instruction. be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that th e power down mode (pof and pof2 instructions) cannot be used when using the external clock. (6) sub-clock gene rating circuit f(x cin ) sub-clock signal f(x cin ) is obtained by exte rnally connecting a quartz-crystal oscillator. connec t this external circuit and a quartz-crystal oscillator to pins x cin and x cout at the shortest distance. a feedback resistor is built in between pins x cin and x cout (figure 65). x cin pin and x cout pin are also used as ports d 6 and d 7 , respectively. the sub-clock oscillation circuit is invalid and the function of ports d 6 and d 7 are valid by setting bit 2 of register rg to ?1?. when sub-clock, ports d 6 and d 7 are not used, connect x cin /d 6 to v ss and leave x cout /d 7 open. fig 64. external clock input circuit fig 65. external quarts-crystal circuit 4559 x in x out external oscillation circuit v dd v ss * do not use the crck instruction in program. 4559 x cin x cout rd c in c out note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the quartz-crystal manufacturer?s recommended value because constants such as capacitance depend on the resonator.
rev.1.04 aug 23, 2007 page 64 of 146 rej03b0188-0104 4559 group (7) clock control register mr register mr controls syst em clock and operation mode (frequency division of system cl ock). set the contents of this register through register a wi th the tmra in struction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. (8) clock control register rg register rg controls th e start/stop of each os cillation circuit. set the contents of this register through register a with the trga instruction. note 1. r? represents read enabled, and ?w? represents write enabled. note 2. the stopped clock cannot be selected for system clock. note 3. ?11? cannot be set to the low-order 2 bits (mr 1 , mr 0 ) of register mr. note 4. the oscillation circuit select ed for system clock cannot be stopped. table 28 clock control registers clock control register mr at reset : 1100 2 at power down : state retained r/w tamr/tmra mr 3 operation mode selection bits mr 3 mr 2 operation mode 0 0 through mode 0 1 frequency divided by 2 mode mr 2 1 0 frequency divided by 4 mode 1 1 frequency divided by 8 mode mr 1 system clock selection bits (note 2) mr 1 mr 0 system clock 0 0 f(ring) mr 0 0 1 f(x in ) 10f(x cin ) 1 1 not available (note 3) clock control register rg at reset : 000 2 at power down : state retained w trga rg 2 sub-clock (f(x cin )) control bit (note 4) 0 sub-clock (f(x cin )) oscillation available, ports d 6 and d 7 not selected 1 sub-clock (f(x cin )) oscillation stop, ports d 6 and d 7 selected rg 1 main-clock (f(x in )) control bit (note 4) 0 main clock (f(x in )) oscillation available 1 main clock (f(x in )) oscillation stop rg 0 on-chip oscillator (f(ring)) control bit (note 4) 0 on-chip oscillator (f(ring)) oscillation available 1 on-chip oscillator (f(ring)) oscillation stop
rev.1.04 aug 23, 2007 page 65 of 146 rej03b0188-0104 4559 group qzrom writing mode in the qzrom writing mode , the user rom area can be rewritten while the microcomputer is mounted on-board by using a serial pro-grammer which is a pplicable for this microcomputer. table 29 lists the pin descript ion (qzrom writing mode) and figure 66 shows the pin connections. refer to figure 67 for examples of a connection with a serial pro- grammer. contact the manufacturer of y our serial programmer for serial pro-grammer. refer to the user?s manual of your serial programmer for details on how to use it. note 1. note that the p2 0 /seg 24 pin is pulled down internally by the mcu during the transition period (the period when v pp is approximately 0.5 v dd to 1.3 v dd ) when the programming power supply (v pp ) is applied to the cnv ss pin. in addition, the p2 0 /seg 24 pin is high inpedance when v pp is approximately 1.3 v dd or grater. table 29 pin description (qzrom writing mode) pin name i/o function v dd , v ss power source, gnd apply 2.7 to 4.7v to v cc , and 0v to v ss . reset reset input input reset input pin for active ?l?. reset occurs when reset pin is hold at an ?l? level for 16 cycles or more of x in . x in , x cin clock input input either connect an oscillator circuit or connect x in and x cin to v ss and leave x out and x cout open. x out , x cout clock output output d 0 ? d 5 p0 0 /seg 16 ? p0 3 /seg 19 p1 0 /seg 20 ? p1 3 /seg 23 p2 0 /seg 24 (note 1) ? p2 3 /seg 27 p3 0 /seg 28 ? p3 3 /seg 31 i/o port i/o input ?h? or ?l? level signal or leave the pin open. cnv ss v pp input input qzrom programmable power source pin. d 4 sda input/output i/o serial data i/o pin. d 3 sclk input input serial clock input pin. d 2 pgm input input read/program pulse input pin. vdce voltage drop detection circuit enable input input ?h? or ?l? level signal seg 0 /v lc3 ? seg 2 /v lc1 seg 3 ? seg 15 com 0 ? com 3 segment output/ lcd power source/ common output output either connect to an lcd panel or leave open. c/cntr output port c/ timer i/o output c/cntr pin outputs ?l? level.
rev.1.04 aug 23, 2007 page 66 of 146 rej03b0188-0104 4559 group fig 66. pin connection diagram outline plqp0052ja-a (52p6a-a) 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 40 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 d 2 d 3 d 4 d 5 /int cnvss x cin /d 6 x cout /d 7 reset x out vss x in v dd c/cntr p1 0 /seg 20 p0 3 /seg 19 p0 2 /seg 18 p0 1 /seg 17 p0 0 /seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 seg 7 seg 6 seg 5 seg 4 seg 3 seg 2 /v lc1 seg 1 /v lc2 seg 0 /v lc3 com 3 com 2 com 1 com 0 vdce p1 1 /seg 21 p1 2 /seg 22 p1 3 /seg 23 (note) p2 0 /seg 24 p2 1 /seg 25 p2 2 /seg 26 p2 3 /seg 27 p3 0 /seg 28 p3 1 /seg 29 p3 2 /seg 30 p3 3 /seg 31 d 0 d 1 m34559g6fp m34559g6-xxxfp pin configuration (top view) ? pgm 1k ? *: connect an oscillation circuit : qzrom pin sclk sda v pp v dd v ss note: note that the p2 0 /seg 24 pin is pulled down internally by the mcu during the transition period (that period when v pp is approximately 0.5 v dd to 1.3 v dd ) when the programming power supply (v pp ) is applied to the cnv ss pin. in addition, the p2 0 /seg 24 pin is high impedance when v pp is approximately 1.3 v dd or greater.
rev.1.04 aug 23, 2007 page 67 of 146 rej03b0188-0104 4559 group fig 67. when using programmer of suisei electronics system co., ltd, connection example 4559 group t_vdd t_vpp t_sclk t_pgm/oe / md t_reset gn d reset circuit vcc cnv ss d 4 (sda) reset vss x in x out 4.7 k ? t_rxd t_txd 1k ? t_ busy d 3 (sclk) d 2 (pgm) n.c. set the same termination as the single-chip mode. note: for the programming circuit, the wiring capacity of each signal pin must not exceed 47 pf.
rev.1.04 aug 23, 2007 page 68 of 146 rej03b0188-0104 4559 group list of precautions (1) noise and latch-up prevention connect a capacitor on the following condition to prevent noise and latch-up; ? connect a bypass capacitor (approx. 0.1 f) between pins v dd and v ss at the shortest distance, ? equalize its wiring in width and length, and ? use relatively thick wire. cnv ss is also used as v pp pin. accordingly, when using this pin, connect this pin to v ss through a resistor about 5k ? (connect this resistor to cnv ss /v pp pin as close as possible). (2) note on power source voltage when the power source voltage va lue of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the s upply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. (3) register initial values 1 the initial value of the following registers are undefined after system is released from reset. af ter system is released from reset, set initial values. ? register z (2 bits) ? register d (3 bits) ? register e (8 bits) (4) register initial values 2 the initial value of the followi ng registers are undefined at ram back-up. after system is returned from ram back-up, set initial values. ? register z (2 bits) ? register x (4 bits) ? register y (4 bits) ? register d (3 bits) ? register e (8 bits) (5) program counter make sure that the pc h does not specify after the last page of the built-in rom. (6) stack registers (sks) stack registers (sks) are eight identical registers, so that subroutines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be careful not to over the stack when performing these operations together. (7) multifunction ? the input/output of d 5 can be used even when int is used. be careful when using inputs of both int and d 5 since the input threshold value of int pin is different from that of port d 5 . ? ?h? output function of port c can be used even when the cntr (output) is used. (8) power-on reset when the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 v to the minimum voltage of recommended operati ng conditions to 100 s or less. if the rising time exceeds 100 s, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply voltage reaches the minimum operating voltage. (9) pof, pof2 instruction when the pof or pof2 instru ction is executed continuously after the epof instruction, system enters the ram back-up state. note that system cannot enter the ram back-up state when executing only the pof or pof2 instruction. be sure to disable interrupts by executing the di instruction before executing the epof instruction and the pof/pof2 instruction continuously.
rev.1.04 aug 23, 2007 page 69 of 146 rej03b0188-0104 4559 group (10)d 5 /int pin (1) bit 3 of register i1 when the input of the d 5 /int pin is controlled with the bit 3 of register i1 in software, be careful about the following notes. ? depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 3 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 68.) and then, change the bit 3 of register i1. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at l east one instruction (refer to (2) in figure 68.). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 68.). fig 68. external 0 interrupt program example-1 (2) bit 3 of register i1 when the bit 3 of register i1 is cleared to ?0?, the power down mode is selected and the input of int pin is disabled, be careful about the following notes. ? when the int pin input is disabled (register i1 3 = ?0?), set the key-on wakeup of int pin to be invalid (register k2 0 = ?0?) before system enters to the power down mode. (refer to (1) in figure 69.). fig 69. external 0 interrupt program example-2 (3) bit 2 of register i1 when the interrupt valid waveform of the d 5 /int pin is changed with the bit 2 of regist er i1 in software, be careful about the following notes. ? depending on the input state of the d 5 /int pin, the external 0 interrupt request flag (exf0) may be set when the bit 2 of register i1 is changed. in or der to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register v1 to ?0? (refer to (1) in figure 70.) and then, cha nge the bit 2 of register i1 is changed. in addition, execute the snz0 instruction to clear the exf0 flag to ?0? after executing at least one instruction (refer to (2) in figure 70.). also, set the nop instruction for the case when a skip is performed with the snz0 instru ction (refer to (3) in figure 70.). fig 70. external 0 interrupt program example-3 ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ...... (1) la 8 ; (1 2 ) ti1a ; control of int pin input is changed nop ...................................................... (2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop ...................................................... (3) ? ? ? : these bits are not used here. ? ? ? la 0 ; ( 0 2 ) tk2a ; int0 key-on wakeup disabled .....(1) di epof pof2 ; ram back-up ? ? ? : these bits are not used here. ? ? ? la 4 ; ( 0 2 ) tv1a ; the snz0 instruction is valid ......(1) la 12 ; ( 1 2 ) ti1a ; interrupt valid waveform is changed nop .......................................................(2) snz0 ; the snz0 instruction is executed (exf0 flag cleared) nop .......................................................(3) ? ? ? : these bits are not used here.
rev.1.04 aug 23, 2007 page 70 of 146 rej03b0188-0104 4559 group (11)prescaler stop prescaler counting and then execute the tabps instruction to read its data. stop prescaler counting and then execute the tpsab instruction to write data to prescaler. (12)timer count source stop timer 1, 2 or lc counti ng to change its count source. (13)reading the count value stop timer 1 or 2 counting and then execute the tab1 or tab2 instruction to read its data. (14)writing to the timer stop timer 1, 2 or lc counting and then execute the t1ab, t2ab, t2r2l or tlca instruction to write data to timer. (15)writing to reload register in order to write a data to the reload register r1 while the timer 1 is operating, execute the tr 1ab instruction except a timing of the timer 1 underflow. in order to write a data to the reload register r2h while the timer 2 is operating, execute the t3hab instruction except a timing of the timer 2 underflow. (16)pwm signal if the timer 2 count stop timing and the timer 2 underflow timing overlap during output of the pwm signal, a hazard may occur in the pwm output waveform. when ?h? interval expansion function of the pwm signal is used, set ?1? or more to reload register r2h. set the port c output latch to ?0 ? to output the pwm signal from c/cntr pin. (17)timer 3 stop timer 3 counting to change its count source. when operating timer 3 during cl ock operating mode, set 1 cycle or more of count source to th e following period; from setting bit 2 of register w3 to ?1? till executing the pof instruction. (18)prescaler, timer 1 count start timing and count time when operation starts count starts from the first rising edge of the count source (2) in figure 71 after prescaler and ti mer operations start (1) in figure 71. time to first underflow (3) in figu re 71 is shorter (for up to 1 period of the count source) than time among next underflow (4) in figure 71 by the timing to start the timer and count source operations after count starts. when selecting cntr input as the count source of timer 1, timer 1 operates synchronizing with th e count edge (falling edge or rising edge) of cntr input selected by software. fig 71. timer count start timing and count time when operation starts (1) (19)timer 2, lc count start timing and count time when operation starts count starts from the first edge of the count source (2) in figure 68 after timer 2 and lc operation start (1) in figure 72. time to first underflow (3) in figure 68 is different (for up to 1 period of the count source) fro m time among next underflow (4) in figure 72 by the timing to start the timer and count source operations after count starts. fig 72. timer count start timing and count time when operation starts (2) count source (3) (4) (1) timer start (2) count source (when falling edge of cntr input is selected) timer 1 value timer 1 underflow signal 32 1 0 3 2 1 0 3 2 count source (3) (4) (1) timer start (2) timer value timer underflow signal 32 1 0 3 2 1 0 3 2
rev.1.04 aug 23, 2007 page 71 of 146 rej03b0188-0104 4559 group (20)watchdog timer ? the watchdog timer function is valid after system is released from reset. when not usi ng the watchdog timer function, execute the dwdt instructio n and the wrst instruction continuously, and clear the wef flag to ?0? to stop the watchdog timer function. ? the contents of wdf1 flag and timer wdt are initialized at the power down. ? when using the watchdog timer and the power down, initialize the wdf1 flag with the wrst instruction just before the microcomputer enters the power down mode. also, set the nop instruction after the wrst instruction, for the case when a skip is performed with the wrst instruction. (21)voltage drop detection circuit the voltage drop detection circ uit detection voltage of this product is set up lower than th e minimum value of the supply voltage of the recomme nded operating conditions. when the supply voltage of a mic rocomputer falls below to the minimum value of recommende d operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the fo llowing case may cause program failure (figure 73); supply voltage does not fall below to v rst - , and its voltage re- goes up with no reset. in such a case, please design a system which supply voltage is once reduced below to v rst - and re-goes up after that. fig 73. v dd and v rst - (22)on-chip oscillator the clock frequency of the on-chip oscillator depends on the supply voltage and the ope ration temperature range. be careful that variable frequencies when designing application products. also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. when considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. (23)rc oscillation the crck instruction can be ex ecuted only once after reset release. execute the crck instruction in the initial setting routine (executing it in address 0 in page 0 is recommended). the frequency is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits. (24)external clock be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). also, note that the power-down m ode (pof or pof2 instruction) cannot be used when using the external clock. (25)qzrom (1) be careful not to apply overvoltage to mcu. the contents of qzrom may be overwritte n because of overvoltage. take care especially at turning on the power. (2) as for the product shippe d in blank, renesas does not perform the writing test to user rom area after the assembly process though the qzrom writing test is performed enough before the asse mbly process. therefore, a writing error of approx. 0.1 % may occur. moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing envir onment may cause some writing errors. (26)notes on rom code protect (qzrom product shipped after writing) as for the qzrom product shippe d after writing, the rom code protect is specified according to the rom option setup data in the mask file which is submitted at ordering. the rom option setup data in the mask file is ?00 16 ? for protect enabled or ?ff 16 ? for protect disabled. note that the mask file which has nothing at the rom option data or has the data other than ?00 16 ? and ?ff 16 ? can not be accepted. (27)data required for qzrom writing orders the following are necessary when ordering a qzrom product shipped after writing: 1. qzrom writing confirmation form* 2. mark specification form* 3. rom data...........mask file * for the qzrom writing confirmation form and the mark specification form, refer to th e ?renesas technology corp.? homepage (http://www.ren esas.com/homepage.jsp). note that we cannot de al with special font marking (customer?s trademark etc.) in qzrom microcomputer. v dd v rst + v rst - recommended operating condition min. value v dd v rst + v rst - normal operation reset no reset program failure may occur. recommended operating condition min. value
rev.1.04 aug 23, 2007 page 72 of 146 rej03b0188-0104 4559 group notes on noise countermeasures against noi se are described below. the following counte rmeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. (1) shortest wiring length the wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. the shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) wiring for reset input pin make the length of wiring whic h is connected to the reset input pin as short as possible. especially, connect a capacitor across the reset input pin and the v ss pin with the shortest possible wiring. ?reason in order to reset a microcomput er correctly, 1 machine cycle or more of the width of a pulse input into the reset pin is required. if noise having a shorter pulse wi dth than this is input to the reset input pin, the reset is released before the internal state of the microcomputer is completely initialized. this may cause a program runaway. fig 74. wiring for the reset input pin (2) wiring for cloc k input/output pins ? make the length of wiring which is connected to clock i/o pins as short as possible. ? make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for osc illation from other v ss patterns. fig 75. wiring for clock i/o pins ?reason if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. (3) wiring to cnv ss pin connect an approximately 5 k ? resistor to the v pp pin and also to the gnd pattern supplied to the v ss pin with shortest possible wiring. ?reason the cnv ss pin is the power source input pin for the built-in qzrom. when programming in the built-in qzrom, the impedance of the cnv ss pin is low to allow the electric current for writing flow into the qzrom. because of this, noise can enter easily. if noise enters the cnv ss pin, abnormal instruction codes or data ar e read from the built-in qzrom, which may cause a program runaway. fig 76. wiring for cnv ss pin reset reset circuit noise v ss v ss n.g. reset circuit v ss reset v ss o.k. noise x in x out v ss n.g. x in x out v ss o.k. cnvss v ss the shortest the shortest about 5k ? note: this indicates pin. (note) (note)
rev.1.04 aug 23, 2007 page 73 of 146 rej03b0188-0104 4559 group (2) connection of bypass capacitor across v ss line and v dd line connect an approximately 0.1 f bypass capacitor across the v ss line and the v dd line as follows: ? connect a bypass capacitor across the v ss pin and the v dd pin at equal length. ? connect a bypass capacitor across the v ss pin and the v dd pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v dd line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v dd pin. fig 77. bypass capacitor across the v ss line and the v dd line (3) oscillator concerns take care to prevent an oscillator that generates clocks for a microcomputer operation from bei ng affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and es pecially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. ?reason in the system using a microcomputer, there are signal lines for controlling motors, leds, and th ermal heads or others. when a large current flows through t hose signal lines, strong noise occurs because of mutual inductance. fig 78. wiring for a large current signal line (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a conne cting pattern of an oscillator away from signal lines wher e potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. ?reason signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if su ch lines cross over a clock line, clock waveforms may be de formed, which causes a microcomputer failure or a program runaway. fig 79. wiring to a signal line where potential levels change frequently (3) oscillator protection using v ss pattern as for a two-sided printed circuit board, print a v ss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the v ss pattern to the microcomputer v ss pin with the shortest possible wiring. besides, separate this v ss pattern from other v ss patterns. fig 80. v ss pattern on the underside of an oscillator v ss v dd v ss v dd n.g. o.k. x in x out v ss m microcomputer mutual inductance large current gnd x in x out v ss cntr do not cross n.g. oscillator wiring pattern example an example of v ss patterns on the underside of a printed circuit board separate the v ss line for oscillation from other v ss lines x in x out v ss
rev.1.04 aug 23, 2007 page 74 of 146 rej03b0188-0104 4559 group (4) setup for i/o ports setup i/o ports using hardware and software as follows: ? connect a resistor of 100 ? or more to an i/o port in series. ? as for an input port, read data several times by a program for checking whether input levels are equal or not. ? as for an output port or an i/o port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. ? rewrite data to pull-up contro l registers at fixed periods. (5) providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a so ftware watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective th an program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog time r provided by software. in the following example, to reset a microcomputer to normal operation, the main rout ine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that in terrupt processing is repeated multiple times in a single main routine processing. ? assigns a single word of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main rout ine. the initial value n should satisfy the following condition: n + 1 as the main routine execution cycle may change because of an interrupt processing or ot hers, the initial value n should have a margin. ? watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt processing after the initia l value n has been set. ? detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not ch ange after interrupt processing. ? decrements the swdt conten ts by 1 at each interrupt processing. ? determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). ? detects that the main routine has failed and determines to branch to the program initia lization routine for recovery processing in the following case: if the swdt contents are not in itialized to the initial value n but continued to decrement and if they reach 0 or less. fig 81. watchdog timer by software main routine interrupt processing routine errors (swdt) n ei main processing (swdt) = n? n n interrupt processing routine (swdt) (swdt) ? 1 interrupt processing (swdt) 0? 0 > 0 rti return main routine errors
rev.1.04 aug 23, 2007 page 75 of 146 rej03b0188-0104 4559 group control registers note 1. ?r? represents read enabled, and ?w? represents write enabled. note 2. when the contents of i1 2 and i1 3 are changed, the external interrupt request flag (exf0) may be set. interrupt control register v1 at reset : 0000 2 at power down : 0000 2 r/w tav1/tv1a v1 3 timer 2 interrupt enable bit 0 interrupt disabled (snzt2 instruction is valid) 1 interrupt enabled (snzt2 instruction is invalid) v1 2 timer 1 interrupt enable bit 0 interrupt disabled (snzt1 instruction is valid) 1 interrupt enabled (snzt1 instruction is invalid) v1 1 not used 0 this bit has no function, but read/write is enabled. 1 v1 0 external 0 interrupt enable bit 0 interrupt disabled (snz0 instruction is valid) 1 interrupt enabled (snz0 instruction is invalid) interrupt control register v2 at reset : 0000 2 at power down : 0000 2 r/w tav2/tv2a v2 3 not used 0 this bit has no function, but read/write is enabled. 1 v2 2 not used 0 this bit has no function, but read/write is enabled. 1 v2 1 not used 0 this bit has no function, but read/write is enabled. 1 v2 0 timer 3 interrupt enable bit 0 interrupt disabled (snzt3 instruction is valid) 1 interrupt enabled (snzt3 instruction is invalid) interrupt control register i1 at reset : 0000 2 at power down : state retained r/w tai1/ti1a i1 3 int pin input control bit (note 2) 0 int pin input disabled 1 int pin input enabled i1 2 interrupt valid waveform for int pin/ return level selection bit (note 2) 0 falling waveform (?l? leve l of int pin is recogn ized with the snzi0 instruction)/?l? level 1 rising waveform (?h? level of int pin is recognized with the snzi0 instruction)/?h? level i1 1 int pin edge detection circuit control bit 0 one-sided edge detected 1 both edges detected i1 0 int pin timer 1 count start synchronous circuit selection bit 0 timer 1 count start synchronous circuit not selected 1 timer 1 count start synchronous circuit selected
rev.1.04 aug 23, 2007 page 76 of 146 rej03b0188-0104 4559 group note 1. r? represents read enabled, and ?w? represents write enabled. note 2. the stopped clock cannot be selected for system clock. note 3. ?11? cannot be set to the low-order 2 bits (mr 1 , mr 0 ) of register mr. note 4. the oscillation circuit se lected for system clock cannot be stopped. clock control register mr at reset : 1100 2 at power down : state retained r/w tamr/tmra mr 3 operation mode selection bits mr 3 mr 2 operation mode 0 0 through mode 0 1 frequency divided by 2 mode mr 2 1 0 frequency divided by 4 mode 1 1 frequency divided by 8 mode mr 1 system clock selection bits (note 2) mr 1 mr 0 system clock 0 0 f(ring) mr 0 0 1 f(x in ) 10f(x cin ) 1 1 not available (note 3) clock control register rg at reset : 000 2 at power down : state retained w trga rg 2 sub-clock (f(x cin )) control bit (note 4) 0 sub-clock (f(x cin )) oscillation available, ports d 6 and d 7 not selected 1 sub-clock (f(x cin )) oscillation stop, ports d 6 and d 7 selected rg 1 main-clock (f(x in )) control bit (note 4) 0 main clock (f(x in )) oscillati on available 1 main clock (f(x in )) oscillation stop rg 0 on-chip oscillator (f(ring)) control bit (note 4) 0 on-chip oscillator (f(ring )) oscillati on available 1 on-chip oscillator (f(ring)) oscillation stop
rev.1.04 aug 23, 2007 page 77 of 146 rej03b0188-0104 4559 group note 1. ? r ? represents read enabled, and ? w ? represents write enabled. note 2. this function is valid only when the timer 1 count start sy nchronous circuit is selected (i1 0 = ? 1 ? ). note 3. port c output is invalid when cntr input is selected for the timer 1 count source. timer control register pa at reset : 0 2 at power down : 0 2 w tapp pa 0 prescaler control bit 0 stop (state retained) 1operating timer control register w1 at reset : 0000 2 at power down : state retained r/w taw1/tw1a w1 3 timer 1 count auto-stop circuit selection bit (note 2) 0 timer 1 count auto-stop circuit not selected 1 timer 1 count auto-stop circuit selected w1 2 timer 1 control bit 0 stop (state retained) 1operating timer 1 count source selection bits (note 3) w1 1 w1 0 count source w1 1 0 0 pwm signal (pwmout) 0 1 prescaler output (orclk) 1 0 timer 3 underflow signal (t3udf) w1 0 1 1 cntr input timer control register w2 at reset : 0000 2 at power down : 0000 2 r/w taw2/tw2a w2 3 cntr pin function control bit 0 cntr pin output invalid 1 cntr pin output valid w2 2 pwm signal ?h? interval expansion function control bit 0 pwm signal ?h? interval expansion function invalid 1 pwm signal ?h? interval expansion function valid w2 1 timer 2 control bit 0 stop (state retained) 1 operating w2 0 timer 2 count source selection bit 0x in input 1 prescaler output (orclk)/2 timer control register w3 at reset : 0000 2 at power down : state retained r/w taw3/tw3a w3 3 timer 3 count source selection bit 0x in input 1 prescaler output (orclk) w3 2 timer 3 control bit 0 stop (initial state) 1operating timer 3 count value selection bits w3 1 w3 0 count source w3 1 0 0 underflow every 8192 count 0 1 underflow every 16384 count 1 0 underflow every 32768 count w3 0 1 1 underflow every 65536 count timer control register w4 at reset : 0000 2 at power down : state retained r/w taw4/tw4a w4 3 timer lc control bit 0 stop (state retained) 1 operating w4 2 timer lc count source selection bit 0bit 4 (t3 4 ) of timer 3 1 system clock (stck) w4 1 cntr pin output auto-control circuit selection bit 0 cntr output auto-control circuit not selected 1 cntr output auto-control circuit selected w4 0 cntr pin input count edge selection bit 0 falling edge 1 rising edge
rev.1.04 aug 23, 2007 page 78 of 146 rej03b0188-0104 4559 group note 1. ?r? represents read enabled, and ?w? represents write enabled. note 2. ?r (resistor) multiplied by 3? is used at 1/ 3 bias, and ?r multiplied by 2? is used at 1/2 bias. note 3. v lc3 is connected to v dd internally when seg 0 pin is selected. note 4. use internal dividing resistor when seg 1 and seg 2 pins are selected. lcd control register l1 at reset : 0000 2 at power down : state retained r/w tal1/tl1a l1 3 internal dividing resistor for lcd power supply selection bit (note 2) 0 2r 3, 2r 2 1 r 3, r 2 l1 2 lcd control bit 0 stop (off) 1 operating lcd duty and bias selection bits l1 1 l1 duty bias l1 1 0 0 not available not available 011/2 1/2 101/3 1/3 l1 0 111/4 1/3 lcd control register l2 at reset : 0000 2 at power down : state retained w tl2a l2 3 seg 0 /v lc3 pin function switch bit (note 3) 0 seg 0 1v lc3 l2 2 seg 1 /v lc2 pin function switch bit (note 4) 0 seg 1 1v lc2 l2 1 seg 2 /v lc1 pin function switch bit (note 4) 0 seg 2 1v lc1 l2 0 internal dividing resistor for lcd power supply control bit 0 internal dividing resistor valid 1 internal dividing resistor invalid lcd control register l3 at reset : 1111 2 at power down : state retained w tl3a l3 3 p2 3 /seg 27 pin function switch bit 0 seg 27 1p2 3 l3 2 p2 2 /seg 26 pin function switch bit 0 seg 26 1p2 2 l3 1 p2 1 /seg 25 pin function switch bit 0 seg 25 1p2 1 l3 0 p2 0 /seg 24 pin function switch bit 0 seg 24 1p2 0
rev.1.04 aug 23, 2007 page 79 of 146 rej03b0188-0104 4559 group note 1.?r? represents read enabled, and ?w? represents write enabled. . lcd control register c1 at reset : 1111 2 at power down : state retained w tc1a c1 3 p0 3 /seg 19 pin function switch bit 0 seg 19 1p0 3 c1 2 p0 2 /seg 18 pin function switch bit 0 seg 18 1p0 2 c1 1 p0 1 /seg 17 pin function switch bit 0 seg 17 1p0 1 c1 0 p0 0 /seg 16 pin function switch bit 0 seg 16 1p0 0 lcd control register c2 at reset : 1111 2 at power down : state retained w tc2a c2 3 p1 3 /seg 23 pin function switch bit 0 seg 23 1p1 3 c2 2 p1 2 /seg 22 pin function switch bit 0 seg 22 1p1 2 c2 1 p1 1 /seg 21 pin function switch bit 0 seg 21 1p1 1 c2 0 p1 0 /seg 20 pin function switch bit 0 seg 20 1p1 0 lcd control register c3 at reset : 1111 2 at power down : state retained w tc3a c3 3 p3 3 /seg 31 pin function switch bit 0 seg 31 1p3 3 c3 2 p3 2 /seg 30 pin function switch bit 0 seg 30 1p3 2 c3 1 p3 1 /seg 29 pin function switch bit 0 seg 29 1p3 1 c3 0 p3 0 /seg 28 pin function switch bit 0 seg 28 1p3 0
rev.1.04 aug 23, 2007 page 80 of 146 rej03b0188-0104 4559 group note 1. ?r? represents read enabled, and ?w? represents write enabled. note 2. to be invalid (k2 2 = ?0?) key-on wakeup of ports p3 0 and p3 1 , set the registers k3 0 and k3 1 to ?0.? note 3. to be invalid (k2 3 = ?0?) key-on wakeup of ports p3 2 and p3 3 , set the registers k3 2 and k3 3 to ?0.? key-on wakeup control register k0 at reset : 0000 2 at power down : state retained r/w tak0/tk0a k0 3 ports p1 2 , p1 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 2 ports p1 0 , p1 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 1 ports p0 2 , p0 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k0 0 ports p0 0 , p0 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k1 at reset : 0000 2 at power down : state retained r/w tak1/tk1a k1 3 port p2 3 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 2 port p2 2 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 1 port p2 1 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used k1 0 port p2 0 key-on wakeup control bit 0 key-on wakeup not used 1 key-on wakeup used key-on wakeup control register k2 at reset : 0000 2 at power down : state retained r/w tak2/tk2a k2 3 ports p3 2 , p3 3 key-on wakeup control bit (note 3) 0 key-on wakeup not used 1 key-on wakeup used k2 2 ports p3 0 , p3 1 key-on wakeup control bit (note 2) 0 key-on wakeup not used 1 key-on wakeup used k2 1 int pin return condition selection bit 0 return by level 1 return by edge k2 0 int pin key-on wakeup control bit 0 key-on wakeup invalid 1 key-on wakeup valid key-on wakeup control register k3 at reset : 0000 2 at power down : state retained r/w tak3/tk3a k3 3 ports p3 2 , p3 3 return condition selection bit (note 3) 0 return by level 1 return by edge k3 2 ports p3 2 , p3 3 valid waveform/level selection bit (note 3) 0 falling waveform/?l? level 1 rising waveform/?h? level k3 1 ports p3 0 , p3 1 return condition selection bit (note 2) 0 return by level 1 return by edge k3 0 ports p3 0 , p3 1 valid waveform/level selection bit (note 2) 0 falling waveform/?l? level 1 rising waveform/?h? level
rev.1.04 aug 23, 2007 page 81 of 146 rej03b0188-0104 4559 group note 1. ?r? represents read enabled, and ?w? represents write enabled. pull-up control register pu0 at reset : 0000 2 at power down : state retained r/w tapu0/tpu0a pu0 3 port p0 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 2 port p0 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 1 port p0 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu0 0 port p0 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu1 at reset : 0000 2 at power down : state retained r/w tapu1/tpu1a pu1 3 port p1 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 2 port p1 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 1 port p1 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu1 0 port p1 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu2 at reset : 0000 2 at power down : state retained r/w tapu2/tpu2a pu2 3 port p2 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 2 port p2 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 1 port p2 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu2 0 port p2 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pull-up control register pu3 at reset : 0000 2 at power down : state retained r/w tapu3/tpu3a pu3 3 port p3 3 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 2 port p3 2 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 1 port p3 1 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on pu3 0 port p3 0 pull-up transistor control bit 0 pull-up transistor off 1 pull-up transistor on
rev.1.04 aug 23, 2007 page 82 of 146 rej03b0188-0104 4559 group note 1. ?w? represents write enabled. port output structure control register fr0 at reset : 0000 2 at power down : state retained w tfr0a fr0 3 ports p1 2 , p1 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr0 2 ports p1 0 , p1 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr0 1 ports p0 2 , p0 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr0 0 ports p0 0 , p0 1 output structure selection bit 0 n-channel open-drain output 1 cmos output port output structure control register fr1 at reset : 0000 2 at power down : state retained w tfr1a fr1 3 ports d 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 2 ports d 2 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 1 ports d 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr1 0 ports d 0 output structure selection bit 0 n-channel open-drain output 1 cmos output port output structure control register fr2 at reset : 0000 2 at power down : state retained w tfr2a fr2 3 ports p3 2 , p3 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr2 2 ports p3 0 , p3 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr2 1 ports d 5 output structure selection bit 0 n-channel open-drain output 1 cmos output fr2 0 ports d 4 output structure selection bit 0 n-channel open-drain output 1 cmos output port output structure control register fr3 at reset : 0000 2 at power down : state retained w tfr3a fr3 3 ports p2 3 output structure selection bit 0 n-channel open-drain output 1 cmos output fr3 2 ports p2 2 output structure selection bit 0 n-channel open-drain output 1 cmos output fr3 1 ports p2 1 output structure selection bit 0 n-channel open-drain output 1 cmos output fr3 0 ports p2 0 output structure selection bit 0 n-channel open-drain output 1 cmos output
rev.1.04 aug 23, 2007 page 83 of 146 rej03b0188-0104 4559 group instructions each instruction is described as follows; 1. index list of in struction function 2. machine instructi ons (index by alphabet) 3. machine instructi ons (index by function) 4. instruction code table the symbols shown below are used in the following list of instruction function and the machine instructions. note 1. the 4559 group just invalidates the next instruction when a skip is performed. the contents of program counter is not in creased by 2. accordingly, the number of cycles does not change even if skip is not per formed. however, the cycle count becomes ?1? if the tabp p, rt, or rts instruction is skipped. symbol symbol contents symbol contents a register a (4 bits) r2h timer 2 reload register (8 bits) b register b (4 bits) rlc timer lc reload register (4 bits) dr register dr (3 bits) ps prescaler e register e (8 bits) t1 timer 1 v1 interrupt control register v1 (4 bits) t2 timer 2 v2 interrupt control register v2 (4 bits) tlc timer lc i1 interrupt control register i1 (4 bits) t1f timer 1 interrupt request flag pa timer control register pa (1 bit) t2f timer 2 interrupt request flag w1 timer control register w1 (4 bits) t3f timer 3 interrupt request flag w2 timer control register w2 (4 bits) wdf1 watchdog timer flag w3 timer control register w3 (4 bits) wef watchdog timer enable flag w4 timer control register w4 (4 bits) inte interrupt enable flag mr clock control register mr (4 bits ) exf0 external 0 interrupt request flag rg clock control register rg (3 bits) vdf voltage dr op detection circuit flag l1 lcd control register l1 (4 bits) p power down flag l2 lcd control register l2 (4 bits) d port d (8 bits) l3 lcd control register l3 (4 bits) p0 port p0 (4 bits) c1 lcd control register c1 (4 bits) p1 port p1 (4 bits) c2 lcd control register c2 (4 bits) p2 port p2 (4 bits) c3 lcd control register c3 (4 bits) p3 port p3 (4 bits) k0 key-on wakeup control register k0 (4 bits) c port c (1 bit) k1 key-on wakeup control register k1 (4 bits) int int pin (1 bit) k2 key-on wakeup control register k2 (4 bits) k3 key-on wakeup control register k3 (4 bits) x hexadecimal variable pu0 pull-up control register pu0 (4 bits) y hexadecimal variable pu1 pull-up control register pu1 (4 bits) z hexadecimal variable pu2 pull-up control register pu2 (4 bits) p hexadecimal variable pu3 pull-up control register pu3 (4 bits) n hexadecimal constant fr0 port output structure control regist er fr0 (4 bits) i hexadecimal constant fr1 port output structure control regist er fr1 (4 bits) j hexadecimal constant fr2 port output structure control register fr2 (4 bits) a 3 a 2 a 1 a 0 binary notation of hexadecimal variable a (same for others) fr3 port output structure control register fr3 (4 bits) x register x (4 bits) direction of data movement y register y (4 bits) ( ) contents of registers and memories z register z (2 bits) ? negate, flag unchanged after executing instruction dp data pointer (10 bits) (it consists of registers x, y, and z) m (dp) ram address pointed by the data pointer a label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 pc program counter (14 bits) p, a label indicating address a 6 a 5 a 4 a 3 a 2 a 1 a 0 in page p 6 p 5 p 4 p 3 p 2 p 1 p 0 pc h high-order 7 bits of program counter pc l low-order 7 bits of program counter sk stack register (14 bits 8) c+x hex. c + hex. number x (also same for others) sp stack pointer (3 bits) ? deci sion of state shown before ??? cy carry flag data exchange between a register and memory uptf high-order bit reference enable flag rps prescaler reload register (8 bits) r1 timer 1 reload register (8 bits) r2l timer 2 reload register (8 bits)
rev.1.04 aug 23, 2007 page 84 of 146 rej03b0188-0104 4559 group p=0 to 47 index list of instruction function group- ing mnemonic function page register to register transfer tab (a) (b) 103 122 tba (b) (a) 110 122 tay (a) (y) 110 122 tya (y) (a) 119 122 teab (e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) 112 122 tabe (b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) 104 122 tda (dr 2 ? dr 0 ) (a 2 ? a 0 ) 111 122 tad (a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 105 122 taz (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 110 122 tax (a) (x) 110 122 tasp (a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 108 122 ram addresses lxy x, y (x) x, x = 0 to 15 (y) y, y = 0 to 15 93 122 lz z (z) z, z = 0 to 3 93 122 iny (y) (y) + 1 92 122 dey (y) (y) ? 1 90 122 ram to register transfer tam j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 106 122 xam j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 120 122 xamd j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 120 122 xami j (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 120 122 tma j (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 115 122 group- ing mnemonic function page arithmetic operation la n (a) n n = 0 to 15 92 124 tabp p (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) (uptf) = 1, (dr 2 ) 0 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (b) (rom(pc)) 7 ? 4 (a) (rom(pc)) 3 ? 0 (pc) (sk(sp)) (sp) (sp) ? 1 104 124 am (a) (a) + (m(dp)) 87 124 amc (a) (a) + (m(dp)) + (cy) (cy) carry 87 124 a n (a) (a) + n n = 0 to 15 87 124 and (a) (a)and(m(dp)) 87 124 or (a) (a)or(m(dp)) 94 124 sc (cy) 1 98 124 rc (cy) 0 96 124 szc (cy) = 0 ? 102 124 cma (a) (a) 89 124 rar 95 124 bit operation sb j (mj(dp)) 1 j = 0 to 3 97 124 rb j (mj(dp)) 0 j = 0 to 3 95 124 szb j (mj(dp)) = 0 ? j = 0 to 3 101 124 comparison operation seam (a) = (m(dp)) ? 99 126 sea n (a) = n ? n = 0 to 15 98 126 branch operation b a (pc l ) a 6 ? a 0 88 126 bl p, a (pc h ) p (pc l ) a 6 ? a 0 88 126 bla p (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 88 126 cy a 3 a 2 a 1 a 0
rev.1.04 aug 23, 2007 page 85 of 146 rej03b0188-0104 4559 group p=0 to 47 index list of instruction function (continued) group- ing mnemonic function page subroutine operation bm a (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 88 126 bml p, a (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 ? a 0 89 126 bmla p (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 89 126 return operation rti (pc) (sk(sp)) (sp) (sp) ? 1 97 126 rt (pc) (sk(sp)) (sp) (sp) ? 1 96 126 rts (pc) (sk(sp)) (sp) (sp) ? 1 97 126 interrupt operation di (inte) 0 90 128 ei (inte) 1 91 128 snz0 v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : snz0 = nop 99 128 snzi0 i1 2 = 0 : (int) = ?l? ? i1 2 = 1 : (int) = ?h? ? 99 128 tav1 (a) (v1) 108 128 tv1a (v1) (a) 118 128 tav2 (a) (v2) 108 128 tv2a (v2) (a) 118 128 tai1 (a) (i1) 105 128 ti1a (i1) (a) 113 128 group- ing mnemonic function page timer operation tpaa (pa) (a) 116 128 taw1 (a) (w1) 109 128 tw1a (w1) (a) 118 128 taw2 (a) (w2) 109 128 tw2a (w2) (a) 118 128 taw3 (a) (w3) 109 128 tw3a (w3) (a) 119 128 taw4 (a) (w4) 109 128 tw4a (w4) (a) 119 128 tabps (b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) 104 130 tpsab (rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) 116 130 tab1 (b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) 103 130 t1ab (r1 7 ? r1 4 ) (b) (t1 7 ? t1 4 ) (b) (r1 3 ? r1 0 ) (a) (t1 3 ? t1 0 ) (a) 102 130 tr1ab (r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) 117 130 tab2 (b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) 104 130 t2ab (r2l 7 ? r2l 4 ) (b) (t2 7 ? t2 4 ) (b) (r2l 3 ? r2l 0 ) (a) (t2 3 ? t2 0 ) (a) 102 130 t2r2l (t2 7 ? t2 0 ) (r2l 7 ? r2l 0 ) 103 130 t2hab (r2h 7 ? r2h 4 ) (b) (r2h 3 ? r2h 0 ) (a) 103 130
rev.1.04 aug 23, 2007 page 86 of 146 rej03b0188-0104 4559 group index list of instruction function (continued) group- ing mnemonic function page timer operation tlca (rlc) (a) (tlc) (a) 115 130 snzt1 v1 2 = 0 : (t1f) = 1 ? (t1f) 0 v1 2 = 1 : snzt1=nop 100 130 snzt2 v1 3 = 0 : (t2f) = 1 ? (t2f) 0 v1 3 = 1 : snzt2=nop 100 130 snzt3 v2 0 = 0 : (t3f) = 1 ? (t3f) 0 v2 0 = 1 : snzt3=nop 100 130 input/output operation iap0 (a) (p0) 91 132 op0a (p0) (a) 93 132 iap1 (a) (p1) 91 132 op1a (p1) (a) 94 132 iap2 (a) (p2) 92 132 op2a (p2) (a) 94 132 iap3 (a) (p3) 92 132 op3a (p3) (a) 94 132 cld (d) 1 89 132 rd (d(y)) 0, (y) = 0 to 7 96 132 sd (d(y)) 1, (y) = 0 to 7 98 132 szd (d(y)) = 0 ?, (y) = 0 to 5 102 132 rcp (c) 0 96 132 scp (c) 1 98 132 tfr0a (fr0) (a) 112 132 tfr1a (fr1) (a) 112 132 tfr2a (fr2) (a) 112 132 tfr3a (fr3) (a) 113 132 tapu0 (a) (pu0) 107 132 tpu0a (pu0) (a) 116 132 tapu1 (a) (pu1) 107 132 tpu1a (pu1) (a) 116 132 tapu2 (a) (pu2) 107 132 tpu2a (pu2) (a) 117 132 tapu3 (a) (pu3) 108 132 group- ing mnemonic function page input/output operation tpu3a (pu3) (a) 117 132 tak0 (a) (k0) 105 134 tk0a (k0) (a) 113 134 tak1 (a) (k1) 105 134 tk1a (k1) (a) 113 134 tak2 (a) (k2) 106 134 tk2a (k2) (a) 114 134 tak3 (a) (k3) 106 134 tk3a (k3) (a) 114 134 lcd operation tal1 (a) (l1) 106 134 tl1a (l1) (a) 114 134 tl2a (l2) (a) 114 134 tl3a (l3) (a) 115 134 tc1a (c1) (a) 111 134 tc2a (c2) (a) 111 134 tc3a (c3) (a) 111 134 clock operation crck rc oscillation selected 90 134 tamr (a) (mr) 107 134 tmra (mr) (a) 115 134 trga (rg 2 ? rg 0 ) (a 2 ? a 0 ) 117 134 other operation nop (pc) (pc)+1 93 136 pof transition to clock operating 95 136 pof2 transition to ram back-up 95 136 epof pof or pof2 instruction 91 136 snzp (p) = 1 ? 99 136 snzvd (vdf) = 1? 100 136 wrst (wdf1) = 1 ? (wdf1) 0 119 136 dwdt stop of watchdog timer func- tion enabled 90 136 srst system reset 101 136 rupt (uptf) 0 97 136 supt (uptf) 1 101 136 svde at power down mode, volt- age drop detection circuit valid 101 136
rev.1.04 aug 23, 2007 page 87 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) a n (add n and accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 000110nnnn 2 06n 16 1 1 - overflow = 0 opera- tion: (a) (a) + n n = 0 to 15 grouping: arithmetic operation description: adds the value n in t he immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction w hen there is overflow as the result of operation. am (add accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001010 2 00a 16 11 - - opera- tion: (a) (a)?{(m(dp)) grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. amc (add accumulator, memory and carry) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001011 2 00b 16 110/1 - opera- tion: (a) (a) + (m(dp)) + (cy) (cy) carry grouping: arithmetic operation description: adds the contents of m( dp) and carry flag cy to register a. stores the result in register a and carry flag cy. and (logical and between accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011000 2 018 16 11 - - opera- tion: (a) (a) and (m(dp)) grouping: arithmetic operation description: takes the and operati on between the contents of register a and the contents of m(dp), and stores the result in regis- ter a.
rev.1.04 aug 23, 2007 page 88 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) b a (branch to address a) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 1 8 +a a 16 11 - - opera- tion: (pc l ) a 6 to a 0 grouping: branch operation description: branch within a page : branches to address a in the identi- cal page. note: specify the branch address within the page including this instruction. bl p,a (branch long to address a in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00111p 4 p 3 p 2 p 1 p 0 2 0 e +p p 16 2 2 - - 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 2aa 16 grouping: branch operation description: branch out of a page : branches to address a in page p. note: p = 0 to 47 opera- tion: (pc h ) p (pc l ) a 6 to a 0 bla p (branch long to address (d)+(a) in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010000 2 010 16 22 - - 10p 5 p 4 00p 3 p 2 p 1 p 0 2 2pp 16 grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p = 0 to 47 opera- tion: (pc h ) p (pc l ) (dr 2 ? r 0 , a 3 ? a 0 ) bm a (branch and mark to address a in page 2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 1aa 16 11 - - opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to another page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8.
rev.1.04 aug 23, 2007 page 89 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) bml p,a (branch and mark long to address a in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00110p 4 p 3 p 2 p 1 p 0 2 0 c + p p 16 22 - - 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2 2aa 16 grouping: subroutine call operation description: call the subroutine : ca lls the subroutine at address a in page p. note: p = 0 to 47 be careful not to over the stack because the maximum level of subroutine nesting is 8. opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 ? a 0 bmla p (branch and mark long to address (d)+(a) in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000110000 2 030 16 22 - - 10p 5 p 4 00p 3 p 2 p 1 p 0 2 2pp 16 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p = 0 to 47 be careful not to over the stack because the maximum level of subroutine nesting is 8. opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) cld (clear port d) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010001 2 011 16 11 - - opera- tion: (d) 1 grouping: input/output operation description: sets (1) to port d. cma (complement of accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011100 2 01c 16 11 - - opera- tion: (a) (a ) grouping: arithmetic operation description: stores the one?s complement for register a?s contents in register a.
rev.1.04 aug 23, 2007 page 90 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) crck (clock select: rc oscillation clock) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010011011 2 29b 16 11 - - opera- tion: rc oscillation circuit selected grouping: clock control operation description: selects the rc oscill ation circuit for main clock f(x in ). dey (decrement register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010111 2 017 16 1 1 - (y) = 15 opera- tion: (y) (y) ? 1 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. di (disable interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000100 2 004 16 11 - - opera- tion: (inte) 0 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by ex ecuting the di instruction after executing 1 machine cycle. dwdt (disable watchdog timer) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010011100 2 29c 16 11 - - opera- tion: stop of watchdog timer function enabled grouping: other operation description: stops the watchdog timer f unction by the wrst instruction after executing the dwdt instruction.
rev.1.04 aug 23, 2007 page 91 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) ei (enable interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000101 2 005 16 11 - - opera- tion: (inte) 1 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei instruction after executing 1 machine cycle. epof (enable pof instruction) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011011 2 05b 16 11 - - opera- tion: pof instruction or pof2 instruction valid grouping: other operation description: makes the immediate af ter pof instruction or pof2 instruction valid by execut ing the epof instruction. iap0 (input accumulator from port p0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100000 2 260 16 11 - - opera- tion: (a) (p0) grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100001 2 261 16 11 - - opera- tion: (a) (p1) grouping: input/output operation description: transfers the input of port p1 to register a.
rev.1.04 aug 23, 2007 page 92 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) iap2 (input accumulator from port p2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100010 2 262 16 11 - - opera- tion: (a) (p2) grouping: input/output operation description: transfers the input of port p2 to the register a. iap3 (input accumulator from port p3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001100011 2 263 16 11 - - opera- tion: (a) (p3) grouping: input/output operation description: transfers the input of port p3 to the register a. iny (increment register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010011 2 013 16 11 - (y) = 0 opera- tion: (y) (y) + 1 grouping: ram addresses description: adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of r egister y is not 0, the next instruction is executed. la n (load n in accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 000111nnnn 2 07n 16 11 - continuous description opera- tion: (a) n n = 0 to 15 grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and exe- cuted, only the first la instruction is executed and other la instructions coded continuously are skipped.
rev.1.04 aug 23, 2007 page 93 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) lxy x,y (load register x and y with x and y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 2 3xy 16 11 - continuous description opera- tion: (x) x x = 0 to 15 (y) y y = 0 to 15 grouping: ram addresses description: loads the value x in t he immediate field to register x, and the value y in the immediate fi eld to register y. when the lxy instructions are c ontinuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. lz z (load register z with z) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010010z 1 z 0 2 04 8 +z 16 1 1 - - opera- tion: (z) z z = 0 to 3 grouping: ram addresses description: loads the value z in t he immediate field to register z. nop (no operation) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000000 2 000 16 11 - - opera- tion: (pc) (pc) + 1 grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. op0a (output port p0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100000 2 220 16 11 - - opera- tion: (p0) (a) grouping: input/output operation description: outputs the contents of register a to port p0.
rev.1.04 aug 23, 2007 page 94 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) op1a (output port p1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100001 2 221 16 11 - - opera- tion: (p1) (a) grouping: input/output operation description: outputs the contents of register a to port p1. op2a (output port p2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100010 2 222 16 11 - - opera- tion: (p2) (a) grouping: input/output operation description: outputs the contents of the register a to port p2. op3a (output port p3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100011 2 223 16 11 - - opera- tion: (p3) (a) grouping: input/output operation description: outputs the contents of the register a to port p3. or (logical or between accumulator and memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011001 2 019 16 11 - - opera- tion: (a) (a) or (m(dp)) grouping: arithmetic operation description: takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a.
rev.1.04 aug 23, 2007 page 95 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) pof (power off) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000010 2 002 16 11 - - opera- tion: transition to clock operating mode grouping: other operation description: puts the system in cl ock operating mode by executing the pof2 instruction after exec uting the epof instruction. note: if the epof instruction is not executed just before this instruction, this instruction is equivalent to the nop instruc- tion. pof2 (power off2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001000 2 008 16 11 - - opera- tion: transition to ram back-up mode grouping: other operation description: puts the system in ra m back-up state by executing the pof2 instruction after exec uting the epof instruction. note: if the epof instruction is not executed before executing this instruction, this instru ction is equivalent to the nop instruction. rar (rotate accumulator right) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011101 2 01d 16 110/1 - opera- tion: grouping: arithmetic operation description: rotates 1 bit of the conten ts of register a including the con- tents of carry flag cy to the right. rb j (reset bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010011 j j 2 04 c +j 16 11 - - opera- tion: (mj(dp)) 0 j = 0 to 3 grouping: bit operation description: clears (0) the contents of bi t j (bit specified by the value j in the immediate field) of m(dp). cy a 3 a 2 a 1 a 0
rev.1.04 aug 23, 2007 page 96 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) rc (reset carry flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000110 2 006 16 110 - opera- tion: (cy) 0 grouping: arithmetic operation description: clears (0) to carry flag cy. rcp (reset port c) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001100 2 28c 16 11 - - opera- tion: (c) 0 grouping: input/output operation description: clears (0) to port c. rd (reset port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010100 2 014 16 11 - - opera- tion: (d(y)) 0 (y) = 0 to 7 grouping: input/output operation description: clears (0) to a bit of port d specified by register y. note: (y) = 0 to 7. do not execute this instructi on if values except above are set to register y. rt (return from subroutine) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000100 2 044 16 12 - - opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from subroutine to the routine called the subrou- tine.
rev.1.04 aug 23, 2007 page 97 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) rti (return from interrupt) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000110 2 046 16 11 - - opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy instruction, register a and register b to the states just before interrupt. rts (return from subroutine and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001000101 2 045 16 1 2 - skip at uncondition opera- tion: (pc) (sk(sp)) (sp) (sp) ? 1 grouping: return operation description: returns from subroutine to the routine called the subrou- tine, and skips the next instruction at uncondition. rupt (reset upt flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011000 2 058 16 11 - - opera- tion: (uptf) 0 grouping: other operation description: clears (0) to the high-or der bit reference enable flag uptf. note: even when the table reference instruction (tabp p) is exe- cuted, the high-order 2 bits of rom reference data is not transferred to register d. sb j (set bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00010111 j j 2 05 c +j 16 11 - - opera- tion: (mj(dp)) 1 j = 0 to 3 grouping: bit operation description: sets (1) the contents of bi t j (bit specified by the value j in the immediate field) of m(dp).
rev.1.04 aug 23, 2007 page 98 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) sc (set carry flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000111 2 007 16 111 - opera- tion: (cy) 1 grouping: arithmetic operation description: sets (1) to carry flag cy. scp (set port c) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001101 2 28d 16 11 - - opera- tion: (c) 1 grouping: input/output operation description: sets (1) to port c. sd (set port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000010101 2 015 16 11 - - opera- tion: (d(y)) 1 (y) = 0 to 7 grouping: input/output operation description: sets (1) to a bit of port d specified by register y. note: (y) = 0 to 7. do not execute this instructi on if values except above are set to register y. sea n (skip equal, accumulator with immediate data n) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100101 2 025 16 22 - (a) = n n = 0 to 15 000111nnnn 2 07n 16 grouping: comparison operation description: skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the val ue n in the immediate field. opera- tion: (a) = n ? n = 0 to 15
rev.1.04 aug 23, 2007 page 99 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) seam (skip equal, accumulator with memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100110 2 026 16 1 1 - (a) = (m(dp)) opera- tion: (a) = (m(dp)) ? grouping: comparison operation description: skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). snz0 (skip if non zero condition of external interrupt 0 request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111000 2 038 16 11 -v1 0 = 0 : (exf0) = 1 opera- tion: v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : snz0 = nop (v1 0 : bit 0 of the interrupt control register v1) grouping: interrupt operation description: when v1 0 = 0 : clears (0) to the exf0 flag and skips the next instruction when exter nal 0 interrupt request flag exf0 is ?1?. when the exf0 flag is ?0?, executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. snzi0 (skip if non zero condition of external interrupt 0 input pin) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111010 2 03a 16 11 - i1 2 = 0 : (int0) = ?l? i1 2 = 1 : (int0) = ?h? opera- tion: i1 2 = 0 : (int) = ?l? ? i1 2 = 1 : (int) = ?h? ? (i1 2 : bit 2 of the interrupt control register i1) grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int pin is ?l?. executes the next instruction when the level of int pin is ?h?. when i1 2 = 1 : skips the next instruction when the level of int pin is ?h.? executes the next instruction when the level of int pin is ?l?. snzp (skip if non zero condition of power down flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000011 2 003 16 11 - (p) = 1 opera- tion: (p) = 1 ? grouping: other operation description: skips the next instruction when the p flag is ?1?. after skipping, the p flag remains unchanged. executes the next instruction when the p flag is ?0?.
rev.1.04 aug 23, 2007 page 100 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) snzt1 (skip if non zero condition of timer 1 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000000 2 280 16 11 -v1 2 = 0 : (t1f) = 1 opera- tion: v1 2 = 0 : (t1f) = 1 ? (t1f) 0 v1 2 = 1 : snzt1 = nop (v1 2 = bit 2 of interrupt control register v1) grouping: timer operation description: when v1 2 = 0 : clears (0) to the t1f flag and skips the next instruction when timer 1 interrupt request flag t1f is ?1?. when the t1f flag is ?0,? executes the next instruction. when v1 2 = 1 : this instruction is equivalent to the nop instruction. snzt2 (skip if non zero condition of timer 2 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000001 2 281 16 11 -v1 3 = 0 : (t2f) = 1 opera- tion: v1 3 = 0 : (t2f) = 1 ? (t2f) 0 v1 3 = 1 : snzt2 = nop (v1 3 = bit 3 of interrupt control register v1) grouping: timer operation description: when v1 3 = 0 : clears (0) to the t2f flag and skips the next instruction when timer 2 interrupt request flag t2f is ?1?. when the t2f flag is ?0?, executes the next instruction. when v1 3 = 1 : this instruction is equivalent to the nop instruction. snzt3 (skip if non zero condition of timer 3 interrupt request flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010000010 2 282 16 11 -v2 0 = 0 : (t3f) = 1 opera- tion: v2 0 = 0 : (t3f) = 1 ? (t3f) 0 v2 0 = 1 : snzt3 = nop grouping: timer operation description: when v2 0 = 0 : clears (0) to the t3f flag and skips the next instruction when timer 3 interrupt request flag t3f is ?1?. when the t3f flag is ?0?, executes the next instruction. when v2 0 = 1 : this instruction is equivalent to the nop instruction. snzvd (skip if non zero condition of voltage detector flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010001010 2 28a 16 11 -v2 3 = 0 : (vdf) = 1 opera- tion: (vdf) = 1? grouping: other operation description: skips the next instruct ion when voltage drop detection cir- cuit flag vdf is ?1?. execute instruction when vdf is ?0?. after skipping, the contents of vdf remains unchanged.
rev.1.04 aug 23, 2007 page 101 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) srst (system reset) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000000001 2 001 16 11 - - opera- tion: system reset grouping: other operation description: system reset occurs. supt (set upt flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001011001 2 059 16 11 - - opera- tion: (uptf) 1 grouping: other operation description: sets (1) to the high- order bit reference enable flag uptf. when the table reference instru ction (tabp p) is executed, the high-order 2 bits of rom reference data is transferred to the low-order 2 bits of register d. svde (set voltage detector enable flag) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010010011 2 293 16 11 - - opera- tion: voltage drop detection circuit valid at powerdown mode. grouping: other operation description: voltage drop detection ci rcuit is valid at powerdown mode (clock operating mode, ram back-up mode) note: this instruction can be used only for h version. szb j (skip if zero, bit) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 00001000 j j 2 02 j 16 11 - (mj(dp)) = 0 j = 0 to 3 opera- tion: (mj(dp)) = 0 ? j = 0 to 3 grouping: bit operation description: skips the next instruction when the contents of bit j (bit specified by the value j in t he immediate field) of m(dp) is ?0?. executes the next instruction when the contents of bit j of m(dp) is ?1?.
rev.1.04 aug 23, 2007 page 102 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) szc (skip if zero, carry flag ) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101111 2 02f 16 11 - (cy) = 0 opera- tion: (cy) = 0 ? grouping: arithmetic operation description: skips the next instruct ion when the contents of carry flag cy is ?0?. after skipping, the cy flag remains unchanged. executes the next instruction when the contents of the cy flag is ?1?. szd (skip if zero, port d specified by register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000100100 2 024 16 2 2 - (d(y)) = 0 0000101011 2 02b 16 grouping: input/output operation description: skips the next instructi on when a bit of port d specified by register y is ?0?. executes t he next instruction when the bit is ?1?. note: (y) = 0 to 5. do not execute this instructi on if values except above are set to register y. opera- tion: (d(y)) = 0 ? (y) = 0 to 5 t1ab (transfer data to timer 1 and register r1 from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110000 2 230 16 11 - - opera- tion: (t1 7 ? t1 4 ) (b) (r1 7 ? r1 4 ) (b) (t1 3 ? t1 0 ) (a) (r1 3 ? r1 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. t2ab (transfer data to timer 2 and register r2l from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110001 2 231 16 11 - - opera- tion: (t2 7 ? t2 4 ) (b) (r2l 7 ? r2l 4 ) (b) (t2 3 ? t2 0 ) (a) (r2l 3 ? r2l 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (t2 7 ? t2 4 ) of timer 2 and the high-order 4 bits (r2l 7 ? r2l 4 ) of timer 2 reload register r2l. transfers the contents of register a to the low-order 4 bits (t2 3 ? t2 0 ) of timer 2 and the low-order 4 bits (r2l 3 ? r2l 0 ) of timer 2 reload register r2.
rev.1.04 aug 23, 2007 page 103 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) t2hab (transfer data to register r2h from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010010100 2 294 16 11 - - opera- tion: (r2h 7 ? r2h 4 ) (b) (r2h 3 ? r2h 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2h. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2h. t2r2l (transfer data to timer 2 from register r2l) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010010101 2 295 16 11 - - opera- tion: (t2 7 ? t2 0 ) (r2l 7 ? r2l 0 ) grouping: timer operation description: transfers the contents of reload register r2l to timer 2. tab (transfer data to accumulator from register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011110 2 01e 16 11 - - opera- tion: (a) (b) grouping: register to register transfer description: transfers the contents of register b to register a. tab1 (transfer data to accumulato r and register b from timer 1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110000 2 270 16 11 - - opera- tion: (b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) grouping: timer operation description: transfers the high-order 4 bits (t1 7 ? t1 4 ) of timer 1 to reg- ister b. transfers the low-order 4 bits (t1 3 ? t1 0 ) of timer 1 to regis- ter a.
rev.1.04 aug 23, 2007 page 104 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tab2 (transfer data to accumulato r and register b from timer 2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110001 2 271 16 11 - - opera- tion: (b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) grouping: timer operation description: transfers the high-order 4 bits (t2 7 ? t2 4 ) of timer 2 to reg- ister b. transfers the low-order 4 bits (t2 3 ? t2 0 ) of timer 2 to regis- ter a. tabe (transfer data to accumulator and register b from register e) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101010 2 02a 16 11 - - opera- tion: (b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) grouping: register to register transfer description: transfers the high-order 4 bits (e 7 ? e 4 ) of register e to reg- ister b, and low-order 4 bits of register e to register a. tabp p (transfer data to accumulator and register b from program memory in page p) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0010p 5 p 4 p 3 p 2 p 1 p 0 2 0 8 +p p 16 1 3 - - opera- tion: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) (b) (rom(pc)) 7 ? 4 (a) (rom(pc)) 3 ? 0 (uptf) 1 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (dr 2 ) 0 (pc) (sk(sp)) (sp) (sp) ? 1 grouping: arithmetic operation description: transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when uptf is 1, transfers bits 9, 8 to the low- order 2 bits (dr 1 , dr 0 ) of register d, and ?0? is stored to the least significant bit (dr 2 ) of register d. when this instruction is executed, 1 st age of stack register (sk) is used. note: p = 0 to 47 when this instruction is executed, be ca reful not to over the stack because 1 stage of stack register is used. tabps (transfer data to accumulator and register b from pre-scaler) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001110101 2 275 16 11 - - opera- tion: (b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) grouping: timer operation description: transfers the high-order 4 bits of prescaler to register b. transfers the low-order 4 bits of prescaler to register a.
rev.1.04 aug 23, 2007 page 105 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tad (transfer data to accumulator from register d) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010001 2 051 16 11 - - opera- tion: (a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. tai1 (transfer data to accumulator from register i1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010011 2 253 16 11 - - opera- tion: (a) (i1) grouping: interrupt operation description: transfers the contents of interrupt control register i1 to reg- ister a. tak0 (transfer data to accumu lator from register k0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010110 2 256 16 11 - - opera- tion: (a) (k0) grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a. tak1 (transfer data to accumu lator from register k1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011001 2 259 16 11 - - opera- tion: (a) (k1) grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a.
rev.1.04 aug 23, 2007 page 106 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tak2 (transfer data to accumu lator from register k2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011010 2 25a 16 11 - - opera- tion: (a) (k2) grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. tak3 (transfer data to accumu lator from register k3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011011 2 25b 16 11 - - opera- tion: (a) (k3) grouping: input/output operation description: transfers the contents of key-on wakeup control register k3 to register a. tal1 (transfer data to accumulator from register l1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001010 2 24a 16 11 - - opera- tion: (a) (l1) grouping: lcd operation description: transfers the contents of lcd control register l1 to regis- ter a. tam j (transfer data to accumulator from memory) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101100 j j j j 2 2c j 16 11 - - opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x.
rev.1.04 aug 23, 2007 page 107 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tamr (transfer data to accumulator from register mr) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010010 2 252 16 11 - - opera- tion: (a) (mr) grouping: clock operation description: transfers the contents of clock control register mr to reg- ister a. tapu0 (transfer data to accumu lator from register pu0) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001010111 2 257 16 11 - - opera- tion: (a) (pu0) grouping: input/output operation description: transfers the contents of pull-up control register pu0 to register a. tapu1 (transfer data to accumu lator from register pu1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011110 2 25e 16 11 - - opera- tion: (a) (pu1) grouping: input/output operation description: transfers the contents of pull-up control register pu1 to register a. tapu2 (transfer data to accumu lator from register pu2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011111 2 25f 16 11 - - opera- tion: (a) (pu2) grouping: input/output operation description: transfers the contents of pull-up control register pu2 to register a.
rev.1.04 aug 23, 2007 page 108 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tapu3 (transfer data to accumu lator from register pu3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001011101 2 25d 16 11 - - opera- tion: (a) (pu3) grouping: input/output operation description: transfers the contents of pull-up control register pu3 to register a. tasp (transfer data to accumulator from stack pointer) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010000 2 050 16 11 - - opera- tion: (a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low- order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. tav1 (transfer data to accumulator from register v1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010100 2 054 16 11 - - opera- tion: (a) (v1) grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. tav2 (transfer data to accumulator from register v2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010101 2 055 16 11 - - opera- tion: (a) (v2) grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a.
rev.1.04 aug 23, 2007 page 109 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) taw1 (transfer data to accumu lator from register w1) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001011 2 24b 16 11 - - opera- tion: (a) (w1) grouping: timer operation description: transfers the contents of timer control register w1 to regis- ter a. taw2 (transfer data to accumu lator from register w2) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001100 2 24c 16 11 - - opera- tion: (a) (w2) grouping: timer operation description: transfers the contents of timer control register w2 to regis- ter a. taw3 (transfer data to accumu lator from register w3) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001101 2 24d 16 11 - - opera- tion: (a) (w3) grouping: timer operation description: transfers the contents of timer control register w3 to regis- ter a. taw4 (transfer data to accumu lator from register w4) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1001001110 2 24e 16 11 - - opera- tion: (a) (w4) grouping: timer operation description: transfers the contents of timer control register w4 to regis- ter a.
rev.1.04 aug 23, 2007 page 110 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tax (transfer data to accumulator from register x) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010010 2 052 16 11 - - opera- tion: (a) (x) grouping: register to register transfer description: transfers the contents of register x to register a. tay (transfer data to accumulator from register y) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011111 2 01f 16 11 - - opera- tion: (a) (y) grouping: register to register transfer description: transfers the contents of register y to register a. taz (transfer data to accumulator from register z) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0001010011 2 053 16 11 - - opera- tion: (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. tba (transfer data to register b from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001110 2 00e 16 11 - - opera- tion: (b) (a) grouping: register to register transfer description: transfers the contents of register a to register b.
rev.1.04 aug 23, 2007 page 111 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tc1a (transfer data to register c1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010101000 2 2a8 16 11 - - opera- tion: (c1) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister c1. tc2a (transfer data to register c2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010101001 2 2a9 16 11 - - opera- tion: (c2) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister c2. tc3a (transfer data to register c3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000100110 2 226 16 11 - - opera- tion: (c3) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister c3. tda (transfer data to register d from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000101001 2 029 16 11 - - opera- tion: (dr 2 ? dr 0 ) (a 2 ? a 0 ) grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 ? a 0 ) of register a to register d.
rev.1.04 aug 23, 2007 page 112 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) teab (transfer data to register e from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000011010 2 01a 16 11 - - opera- tion: (e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 3 ? e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 ? e 0 ) of register e. tfr0a (transfer data to register fr0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101000 2 228 16 11 - - opera- tion: (fr0) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr0. tfr1a (transfer data to register fr1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101001 2 229 16 11 - - opera- tion: (fr1) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr1. tfr2a (transfer data to register fr2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101010 2 22a 16 11 - - opera- tion: (fr2) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr2.
rev.1.04 aug 23, 2007 page 113 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tfr3a (transfer data to register fr3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101011 2 22b 16 11 - - opera- tion: (fr3) (a) grouping: input/output operation description: transfers the contents of register a to port output structure control register fr3. ti1a (transfer data to register i1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010111 2 217 16 11 - - opera- tion: (i1) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister i1. tk0a (transfer data to register k0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000011011 2 21b 16 11 - - opera- tion: (k0) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k0. tk1a (transfer data to register k1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010100 2 214 16 11 - - opera- tion: (k1) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k1.
rev.1.04 aug 23, 2007 page 114 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tk2a (transfer data to register k2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010101 2 215 16 11 - - opera- tion: (k2) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k2. tk3a (transfer data to register k3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101100 2 22c 16 11 - - opera- tion: (k3) (a) grouping: input/output operation description: transfers the contents of register a to key-on wakeup con- trol register k3. tl1a (transfer data to register l1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001010 2 20a 16 11 - - opera- tion: (l1) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister l1. tl2a (transfer data to register l2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001011 2 20b 16 11 - - opera- tion: (l2) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister l2.
rev.1.04 aug 23, 2007 page 115 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tl3a (transfer data to register l3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001100 2 20c 16 11 - - opera- tion: (l3) (a) grouping: lcd control operation description: transfers the contents of register a to the lcd control reg- ister l3. tlca (transfer data to timer lc and register rlc from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001101 2 20d 16 11 - - opera- tion: (lc) (a) (rlc) (a) grouping: timer control operation description: transfers the contents of register a to timer lc and reload register rlc. tma j (transfer data to memory from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101011 j j j j 2 2b j 16 11 - - opera- tion: (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is performed between register x and the value j in the immediate field, and stores the result in register x. tmra (transfer data to register mr from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010110 2 216 16 11 - - opera- tion: (mr) (a) grouping: clock operation description: transfers the contents of r egister a to clock control register mr.
rev.1.04 aug 23, 2007 page 116 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tpaa (transfer data to register pa from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010101010 2 2aa 16 11 - - opera- tion: (pa 0 ) (a 0 ) grouping: timer operation description: transfers the least si gnificant bit of register a (a 0 ) to timer control register pa. tpsab (transfer data to pre-scaler and regist er rps from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000110101 2 235 16 11 - - opera- tion: (rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps. transfers the contents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. tpu0a (transfer data to register pu0 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101101 2 22d 16 11 - - opera- tion: (pu0) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu0. tpu1a (transfer data to register pu1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101110 2 22e 16 11 - - opera- tion: (pu1) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu1.
rev.1.04 aug 23, 2007 page 117 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tpu2a (transfer data to register pu2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000101111 2 22f 16 11 - - opera- tion: (pu2) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu2. tpu3a (transfer data to register pu3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001000 2 208 16 11 - - opera- tion: (pu3) (a) grouping: input/output operation description: transfers the contents of register a to pull-up control regis- ter pu3. tr1ab (transfer data to register r1 from accumulator and register b) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000111111 2 23f 16 11 - - opera- tion: (r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) grouping: timer control operation description: transfers the contents of register b to the high-order 4 bits (r1 7 ? r1 4 ) of timer 1 reload register r1, and the contents of register a to the low-order 4 bits (r1 3 ? r1 0 ) of timer 1 reload register r1. trga (transfer data to register rg from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001001 2 209 16 11 - - opera- tion: (rg 2 ? rg 0 ) (a 2 ? a 0 ) grouping: clock control operation description: transfers the contents of register a to register rg.
rev.1.04 aug 23, 2007 page 118 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tv1a (transfer data to register v1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111111 2 03f 16 11 - - opera- tion: (v1) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister v1. tv2a (transfer data to register v2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000111110 2 03e 16 11 - - opera- tion: (v2) (a) grouping: interrupt operation description: transfers the contents of register a to interrupt control reg- ister v2. tw1a (transfer data to register w1 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001110 2 20e 16 11 - - opera- tion: (w1) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w1. tw2a (transfer data to register w2 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000001111 2 20f 16 11 - - opera- tion: (w2) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w2.
rev.1.04 aug 23, 2007 page 119 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) tw3a (transfer data to register w3 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010000 2 210 16 11 - - opera- tion: (w3) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w3. tw4a (transfer data to register w4 from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1000010001 2 211 16 11 - - opera- tion: (w4) (a) grouping: timer operation description: transfers the contents of r egister a to timer control register w4. tya (transfer data to register y from accumulator) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 0000001100 2 00c 16 11 - - opera- tion: (y) (a) grouping: register to register transfer description: transfers the contents of register a to register y. wrst (watchdog timer reset) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 1010100000 2 2a0 16 11 - (wdf1) = 1 opera- tion: (wdf1) = 1 ? (wdf1) 0 grouping: other operation description: clears (0) to the wdf1 flag and skips the next instruction when watchdog timer flag wdf1 is ?1?. when the wdf1 flag is ?0?, executes the next instruction. also, stops the watchdog timer function when executing the wrst instruction immediately after the dwdt instruction.
rev.1.04 aug 23, 2007 page 120 of 146 rej03b0188-0104 4559 group machine instructions (index by alphabet) (continued) xam j (exchange accumulator and memory data) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101101 j j j j 2 2d j 16 11 - - opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. xamd j (exchange accumulator and memory data and decrement register y and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101111 j j j j 2 2f j 16 1 1 - (y) = 15 opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. xami j (exchange accumulator and memory data and increment register y and skip) instruc- tion code d 9 d 0 number of words number of cycles flag cy skip condition 101110 j j j j 2 2e j 16 11 - (y) = 0 opera- tion: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 grouping: ram to register transfer description: after exchanging the cont ents of m(dp) with the contents of register a, an exclusive or operation is performed between register x and the val ue j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of r egister y is not 0, the next instruction is executed.
rev.1.04 aug 23, 2007 page 121 of 146 rej03b0188-0104 4559 group
rev.1.04 aug 23, 2007 page 122 of 146 rej03b0188-0104 4559 group machine instructions (index by types) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation register to register transfer tab 000001111001e 1 1(a) (b) tba 000000111000e 1 1(b) (a) tay 000001111101f 1 1(a) (y) tya 000000110000c 1 1(y) (a) teab 000001101001a 1 1(e 7 ? e 4 ) (b) (e 3 ? e 0 ) (a) tabe 000010101002a 1 1(b) (e 7 ? e 4 ) (a) (e 3 ? e 0 ) tda 0000101001029 1 1(dr 2 ? dr 0 ) (a 2 ? a 0 ) tad 0001010001051 1 1(a 2 ? a 0 ) (dr 2 ? dr 0 ) (a 3 ) 0 taz 0001010011053 1 1(a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 tax 0001010010052 1 1(a) (x) tasp 0001010000050 1 1(a 2 ? a 0 ) (sp 2 ? sp 0 ) (a 3 ) 0 ram addresses lxy x, y 1 1 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 3xy 1 1(x) x x = 0 to 15 (y) y y = 0 to 15 lz z 00010010z 1 z 0 048 +z 1 1 (z) z z = 0 to 3 iny 0000010011013 1 1(y) (y) + 1 dey 0000010111017 1 1(y) (y) ? 1 ram to register transfer tam j 101100 j j j j 2cj 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 xam j 101101 j j j j 2dj 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 xamd j 101111 j j j j 2f j 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ? 1 xami j 101110 j j j j 2e j 1 1(a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 tma j 101011 j j j j 2b j 1 1(m(dp)) (a) (x) (x)exor(j) j = 0 to 15 para meter type of instructi ons
rev.1.04 aug 23, 2007 page 123 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? transfers the contents of register b to register a. ?? transfers the contents of register a to register b. ?? transfers the contents of register y to register a. ?? transfers the contents of register a to register y. ?? transfers the contents of register b to the high-order 4 bits (e 3 ? e 0 ) of register e, and the contents of register a to the low-order 4 bits (e 3 ? e 0 ) of register e. ?? transfers the high-order 4 bits (e 7 ? e 4 ) of register e to register b, and low- order 4 bits of register e to register a. ?? transfers the contents of the low-order 3 bits (a 2 ? a 0 ) of register a to register d. ?? transfers the contents of register d to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. ?? transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. ?0? is stored to the high-order 2 bits (a 3 , a 2 ) of register a. ?? transfers the contents of register x to register a. ?? transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 ? a 0 ) of register a. ?0? is stored to the bit 3 (a 3 ) of register a. continuous description ? loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are cont inuously coded and executed, only the first lxy instruction is executed and other lxy instructions c oded continuously are skipped. ?? loads the value z in the immediate field to register z. (y) = 0 ? adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. (y) = 15 ? subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of regi ster y is not 15, the next instruction is executed. ?? after transferring the contents of m(dp) to regist er a, an exclusive or operation is performed between register x and the value j in the immediate fi eld, and stores the result in register x. ?? after exchanging the contents of m(dp) with the cont ents of register a, an ex clusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. (y) = 15 ? after exchanging the contents of m(dp) with the cont ents of register a, an ex clusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of regi ster y is not 15, the next instruction is executed. (y) = 0 ? after exchanging the contents of m(dp) with the cont ents of register a, an ex clusive or operation is performed between register x and the value j in the immed iate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next instruction is skipped. when the c ontents of register y is not 0, the next instruction is executed. ?? after transferring the contents of register a to m(dp), an exclusive or operation is performed between register x and the value j in the immediate fi eld, and stores the result in register x.
rev.1.04 aug 23, 2007 page 124 of 146 rej03b0188-0104 4559 group note 1.m34571g4: p=0 to 31, m34571g6: p=0 to 47 and m34571gd: p=0 to 127. machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation arithmetic operation la n 000111nnnn07n 1 1(a) n n = 0 to 15 tabp p 0010p 5 p 4 p 3 p 2 p 1 p 0 08 +p p 1 3 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pcl) (dr 2 ? dr 0 , a 3 ? a 0 ) (b) (rom(pc)) 7 - 4 (a) (rom(pc)) 3 - 0 (uptf) = 1 (dr 1 , dr 0 ) (rom(pc)) 9 , 8 (dr 2 ) 0 (pc) (sk(sp)) (sp) (sp) ? 1 am 000000101000a 1 1(a) (a) + (m(dp)) amc 000000101100b 1 1(a) (a) + (m(dp)) + (cy) (cy) carry a n 000110nnnn06n 1 1(a) (a) + n n = 0 to 15 and 0000011000018 1 1(a) (a) and (m(dp)) or 0000011001019 1 1(a) (a) or (m(dp)) sc 0000000111007 1 1(cy) 1 rc 0000000110006 1 1(cy) 0 szc 000010111102f 1 1(cy) = 0 ? cma 000001110001c 1 1(a) (a) rar 000001110101d 1 1 bit operation sb j 00010111 j j 05c +j 1 1 (mj(dp)) 1 j = 0 to 3 rb j 00010011 j j 04c +j 1 1 (mj(dp)) 0 j = 0 to 3 szb j 00001000 j j 02 j 1 1(mj(dp)) = 0 ? j = 0 to 3 para meter type of instructi ons cy a 3 a 2 a 1 a 0
rev.1.04 aug 23, 2007 page 125 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description continuous description ? loads the value n in the immedi ate field to register a. when the la instructions are continuously coded and ex ecuted, only the first la instruction is executed and other la instructions c oded continuously are skipped. ?? transfers bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in p age p. when uptf is 1, transfers bits 9, 8 to the low-order 2 bits (dr 1 , dr 0 ) of register d, and ?0? is stored to the least si gnificant bit (dr 2 ) of register d. when this instruction is executed, 1 stage of stack register (sk) is used. ?? adds the contents of m(dp) to register a. stores t he result in register a. the contents of carry flag cy remains unchanged. ? 0/1 adds the contents of m(dp) and carry flag cy to regist er a. stores the result in register a and carry flag cy. overflow = 0 ? adds the value n in the immediate field to r egister a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. ?? takes the and operation between the contents of register a and the contents of m(dp), and stores the result in register a. ?? takes the or operation between the contents of regist er a and the contents of m(dp), and stores the result in register a. ? 1 sets (1) to carry flag cy. ? 0 clears (0) to carry flag cy. (cy) = 0 ? skips the next instruction when the contents of carry fl ag cy is ?0?. executes t he next instruction when the contents of carry flag cy is ?1?. the contents of carry flag cy remains unchanged. ?? stores the one?s complement for register a?s contents in register a. ? 0/1 rotates 1 bit of the contents of register a including the content s of carry flag cy to the right. ?? sets (1) the contents of bit j (bit specified by the value j in the i mmediate field) of m(dp). ?? clears (0) the contents of bit j (bit specified by the value j in the i mmediate field) of m(dp). (mj(dp)) = 0 j = 0 to 3 ? skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?0?. executes the next instruction when the contents of bit j of m(dp) is ?1?.
rev.1.04 aug 23, 2007 page 126 of 146 rej03b0188-0104 4559 group note 1.m34571g4: p=0 to 31, m34571g6: p=0 to 47 and m34571gd: p=0 to 127. machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation comparison operation seam 0000100110026 1 1(a) = (m(dp)) ? sea n 0000100101025 2 2(a) = n ? n = 0 to 15 000111nnnn07n branch operation b a 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 18 +a a1 1(pc l ) a 6 ? a 0 bl p, a 00111p 4 p 3 p 2 p 1 p 0 0e +p p2 2(pc h ) p (note 1) (pc l ) a 6 ? a 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa bla p 0000010000 010 2 2(pc h ) p (note 1) (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 10p 5 p 4 00p 3 p 2 p 1 p 0 2pp subroutine operation bm a 0 1 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 1 1(sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? a 0 bml p, a 00110p 4 p 3 p 2 p 1 p 0 0c +p p 2 2 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pc l ) a 6 ? a 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2aa bmla p 0000110000 030 2 2(sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note 1) (pc l ) (dr 2 ? dr 0 , a 3 ? a 0 ) 10p 5 p 4 00p 3 p 2 p 1 p 0 2pp return operation rti 0001000110046 1 1(pc) (sk(sp)) (sp) (sp) ? 1 rt 0001000100044 1 2(pc) (sk(sp)) (sp) (sp) ? 1 rts 0001000101045 1 2(pc) (sk(sp)) (sp) (sp) ? 1 para meter type of instructi ons
rev.1.04 aug 23, 2007 page 127 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description (a) = (m(dp)) ? skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of r egister a is not equal to the contents of m(dp). (a) = n n = 0 to 15 ? skips the next instruction when the contents of regist er a is equal to the value n in the immediate field. executes the next instruction when t he contents of register a is not equal to the value n in the immediate field. ?? branch within a page : branches to address a in the identical page. ?? branch out of a page : branches to address a in page p. ?? branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. ?? call the subroutine in page 2 : calls the subroutine at address a in page 2. ?? call the subroutine : calls the subroutine at address a in page p. ?? call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. ?? returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry fl ag, skip status, nop mode status by the continuous description of the la/lxy instruction, register a and register b to the states just before interrupt. ?? returns from subroutine to the routine called the subroutine. skip at uncondition ? returns from subroutine to the routine called the subr outine, and skips the next instruction at uncondition.
rev.1.04 aug 23, 2007 page 128 of 146 rej03b0188-0104 4559 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation interrupt operation di 0000000100004 1 1(inte) 0 ei 0000000101005 1 1(inte) 1 snz0 0 000111000038 1 1v1 0 = 0 : (exf0) = 1 ? (exf0) 0 v1 0 = 1 : snz0 = nop snzi0 000011101003a 1 1i1 2 = 0 : (int) = ?l?? i1 2 = 1 : (int) = ?h?? tav1 0001010100054 1 1(a) (v1) tv1a 000011111103f 1 1(v1) (a) tav2 0001010101055 1 1(a) (v2) tv2a 000011111003e 1 1(v2) (a) tai1 1001010011253 1 1(a) (i1) ti1a 1000010111217 1 1(i1) (a) timer operation tpaa 10101010102aa 1 1(pa) (a) taw1 100100101124b 1 1(a) (w1) tw1a 100000111020e 1 1(w1) (a) taw2 100100110024c 1 1(a) (w2) tw2a 100000111120f 1 1(w2) (a) taw3 100100110124d 1 1(a) (w3) tw3a 1000010000210 1 1(w3) (a) taw4 100100111024e 1 1(a) (w4) tw4a 1000010001211 1 1(w4) (a) para meter type of instructi ons
rev.1.04 aug 23, 2007 page 129 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? clears (0) to interrupt enable flag inte, and disables the interrupt. ?? sets (1) to interrupt enable flag inte, and enables the interrupt. v1 0 = 0 : (exf0) = 1 ? when v1 0 = 0 : clears (0) to the exf0 flag and skips the ne xt instruction when external 0 interrupt request flag exf0 is ?1?. when the exf0 flag is ?0?, executes the next instruction. when v1 0 = 1 : this instruction is equival ent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) (int) = ? l ? however, i1 2 = 0 ? when i1 2 = 0 : skips the next instruction when the level of int pin is ?l?. executes the next instruction when the level of int0 pin is ?h?. (int) = ? h ? however, i1 2 = 1 when i1 2 = 1 : skips the next instruction when the level of int pin is ?h?. executes the next instruction when the level of int0 pin is ?l?. (i1 2 : bit 2 of interrupt control register i1) ?? transfers the contents of interrupt control register v1 to register a. ?? transfers the contents of register a to interrupt control register v1. ?? transfers the contents of interrupt control register v2 to register a. ?? transfers the contents of register a to interrupt control register v2. ?? transfers the contents of interrupt control register i1 to register a. ?? transfers the contents of register a to interrupt control register i1. ?? transfers the contents of register a (a 0 ) to timer control register pa. ?? transfers the contents of timer control register w1 to register a. ?? transfers the contents of register a to timer control register w1. ?? transfers the contents of timer control register w2 to register a. ?? transfers the contents of register a to timer control register w2. ?? transfers the contents of timer control register w3 to register a. ?? transfers the contents of register a to timer control register w3. ?? transfers the contents of timer control register w4 to register a. ?? transfers the contents of register a to timer control register w4.
rev.1.04 aug 23, 2007 page 130 of 146 rej03b0188-0104 4559 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation timer operation tabps 1001110101275 1 1(b) (tps 7 ? tps 4 ) (a) (tps 3 ? tps 0 ) tpsab 1000110101235 1 1(rps 7 ? rps 4 ) (b) (tps 7 ? tps 4 ) (b) (rps 3 ? rps 0 ) (a) (tps 3 ? tps 0 ) (a) tab1 1001110000270 1 1(b) (t1 7 ? t1 4 ) (a) (t1 3 ? t1 0 ) t1ab 1000110000230 1 1(r1 7 ? r1 4 ) (b) (t1 7 ? t1 4 ) (b) (r1 3 ? r1 0 ) (a) (t1 3 ? t1 0 ) (a) tr1ab 100011111123f 1 1(r1 7 ? r1 4 ) (b) (r1 3 ? r1 0 ) (a) tab2 1001110001271 1 1(b) (t2 7 ? t2 4 ) (a) (t2 3 ? t2 0 ) t2ab 1000110001231 1 1(r2l 7 ? r2l 4 ) (b) (t2 7 ? t2 4 ) (b) (r2l 3 ? r2l 0 ) (a) (t2 3 ? t2 0 ) (a) t2hab 1010010100294 1 1(r2h 7 ? r2h 4 ) (b) (r2h 3 ? r2h 0 ) (a) t2r2l 1010010101295 1 1(t2 7 ) (r2l) tlca 100000110120d 1 1(rlc) (a) (tlc) (a) snzt1 1010000000280 1 1v1 2 = 0 : (t1f) = 1 ? after skipping, (t1f) 0 v1 2 = 1 : snzt1=nop snzt2 1010000001281 1 1v1 3 = 0 : (t2f) = 1 ? after skipping, (t2f) 0 v1 3 = 1 : snzt2=nop snzt3 1010000010282 1 1v2 0 = 0 : (t3f) = 1 ? after skipping, (t3f) 0 v2 0 = 1 : snzt3=nop para meter type of instructi ons
rev.1.04 aug 23, 2007 page 131 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? transfers the high-order 4 bits of prescaler to register b. transfers the low-order 4 bits of prescaler to register a. ?? transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps. transfers the contents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. ?? transfers the high-order 4 bits (t1 7 ? t1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 ? t1 0 ) of timer 1 to register a. ?? transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1l. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1l. ?? transfers the contents of register b to the high-order 4 bits (r1 7 ? r1 4 ) of reload register r1, and the contents of register a to the low-order 4 bits (r1 3 ? r1 0 ) of reload register r1. ?? transfers the high-order 4 bits (t2 7 ? t2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 ? t2 0 ) of timer 2 to register a. ?? transfers the contents of register b to the high-order 4 bits (r2l 7 ? r2l 4 ) of timer 2 and timer 2 reload register r2l. transfers the contents of register a to the low-order 4 bits (r2l 3 ? r2l 0 ) of timer 2 and timer 2 reload register r2l. ?? transfers the contents of register b to the high-order 4 bits (r2h 7 ? r2h 4 ) of timer 2 and timer 2 reload register r2h. transfers the contents of register a to the low-order 4 bits (r2h 3 ? r2h 0 ) of timer 2 and timer 2 reload register r2h. ?? transfers the contents of timer 2 reload register r2l to timer 2. ?? transfers the contents of register a to timer lc and reload register rlc. v1 2 = 0 : (t1f) = 1 ? when v1 2 = 0 : clears (0) to the t1f flag and skips the next instruction when timer 1 interrupt request flag t1f is ?1?. when the t1f flag is ?0 ?, executes the next instruction. when v1 2 = 1 : this instruction is equiva lent to the nop instruction. (v1 2 : bit 2 of interrupt control register v1) v1 3 = 0 : (t2f) = 1 ? when v1 3 = 0 : clears (0) to the t2f flag and skips the next instruction when timer 2 interrupt request flag t2f is ?1?. when the t2f flag is ?0 ?, executes the next instruction. when v1 3 = 1 : this instruction is equiva lent to the nop instruction. (v1 3 : bit 3 of interrupt control register v1) v2 0 = 0 : (t3f) = 1 ? when v2 0 = 0 : clears (0) to the t3f flag and skips the next instruction when timer 3 interrupt request flag t3f is ?1?. when the t3f flag is ?0 ?, executes the next instruction. when v2 0 = 1 : this instruction is equiva lent to the nop instruction. (v2 0 : bit 0 of interrupt control register v2)
rev.1.04 aug 23, 2007 page 132 of 146 rej03b0188-0104 4559 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation input/output operation iap0 1001100000260 1 1(a) (p0) op0a 1000100000220 1 1(p0) (a) iap1 1001100001261 1 1(a) (p1) op1a 1000100001221 1 1(p1) (a) iap2 1001100010262 1 1(a) (p2) op2a 1000100010222 1 1(p2) (a) iap3 1001100011263 1 1(a) (p3) op3a 1000100011223 1 1(p3) (a) cld 0000010001011 1 1(d) 1 rd 0000010100014 1 1(d(y)) 0 (y) = 0 to 7 sd 0000010101015 1 1(d(y)) 1 (y) = 0 to 7 szd 0000100100024 2 2(d(y)) = 0 ? (y) = 0 to 5 000010101102b rcp 101000110028c 1 1(c) 0 scp 101000110128d 1 1(c) 1 tfr0a 1000101000228 1 1(fr0) (a) tfr1a 1000101001229 1 1(fr1) (a) tfr2a 100010101022a 1 1(fr2) (a) tfr3a 100010101122b 1 1(fr3) (a) tapu0 1001010111257 1 1(a) (pu0) tpu0a 100010110122d 1 1(pu0) (a) tapu1 100101111025e 1 1(a) (pu1) tpu1a 100010111022e 1 1(pu1) (a) tapu2 100101111125f 1 1(a) (pu2) tpu2a 100010111122f 1 1(pu2) (a) tapu3 100101110125d 1 1(a) (pu3) tpu3a 1000001000208 1 1(pu3) (a) para meter type of instructi ons
rev.1.04 aug 23, 2007 page 133 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? transfers the input of port p0 to register a. ?? outputs the contents of register a to port p0. ?? transfers the input of port p1 to register a. ?? outputs the contents of register a to port p1. ?? transfers the input of port p2 to the register a. ?? outputs the contents of the register a to port p2. ?? transfers the input of port p3 to the register a. ?? outputs the contents of the register a to port p3. ?? sets (1) to port d. ?? clears (0) to a bit of port d specified by register y. ?? sets (1) to a bit of port d specified by register y. (d(y)) = 0 y = 0 to 4 ? skips the next instruction when a bit of port d specified by register y is ?0?. executes the next instruction when a bit of port d specifi ed by register y is ?1?. ?? clears (0) to port c. ?? sets (1) to port c. ?? transfers the contents of register a to port output structure control register fr0. ?? transfers the contents of register a to port output structure control register fr1. ?? transfers the contents of register a to port output structure control register fr2. ?? transfers the contents of register a to port output structure control register fr3. ?? transfers the contents of pull-up control register pu0 to register a. ?? transfers the contents of register a to pull-up control register pu0. ?? transfers the contents of pull-up control register pu1 to register a. ?? transfers the contents of register a to pull-up control register pu1. ?? transfers the contents of pull-up control register pu2 to register a. ?? transfers the contents of register a to pull-up control register pu2. ?? transfers the contents of pull-up control register pu3 to register a. ?? transfers the contents of register a to pull-up control register pu3.
rev.1.04 aug 23, 2007 page 134 of 146 rej03b0188-0104 4559 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation input/output operation tak0 1001010110256 1 1(a) (k0) tk0a 100001101121b 1 1(k0) (a) tak1 1001011001259 1 1(a) (k1) tk1a 1000010100214 1 1(k1) (a) tak2 100101101025a 1 1(a) (k2) tk2a 1000010101215 1 1(k2) (a) tak3 100101101125b 1 1(a) (k3) tk3a 100010110022c 1 1(k3) (a) lcd operation tal1 100100101024a 1 1(a) (l1) tl1a 100000101020a 1 1(l1) (a) tl2a 100000101120b 1 1(l2) (a) tl3a 100000110020c 1 1(l3) (a) tc1a 10101010002a8 1 1(c1) (a) tc2a 10101010012a9 1 1(c2) (a) tc3a 1000100110226 1 1(c3) (a) clock operation crck 101001101129b 1 1rc oscillator selected tamr 1001010010252 1 1(a) (mr) tmra 1000010110216 1 1(mr) (a) trga 1000001001209 1 1(rg 2 ? rg 0 ) (a 2 ? a 0 ) para meter type of instructi ons
rev.1.04 aug 23, 2007 page 135 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? transfers the contents of key-on wakeup control register k0 to register a. ?? transfers the contents of register a to key-on wakeup control register k0. ?? transfers the contents of key-on wakeup control register k1 to register a. ?? transfers the contents of register a to key-on wakeup control register k1. ?? transfers the contents of key-on wakeup control register k2 to register a. ?? transfers the contents of register a to key-on wakeup control register k2. ?? transfers the contents of key-on wakeup control register k3 to register a. ?? transfers the contents of register a to key-on wakeup control register k3. ?? transfers the contents of the lcd control register l1 to register a. ?? transfers the contents of register a to the lcd control register l1. ?? transfers the contents of register a to the lcd control register l2. ?? transfers the contents of register a to the lcd control register l3. ?? transfers the contents of register a to the lcd control register c1. ?? transfers the contents of register a to the lcd control register c2. ?? transfers the contents of register a to the lcd control register c3. ?? selects the rc oscillation circuit for main clock, st ops the on-chip oscillator (internal oscillator). ?? transfers the contents of clock c ontrol regiser mr to register a. ?? transfers the contents of register a to clock control register mr. ?? transfers the contents of register a to clock control register rg.
rev.1.04 aug 23, 2007 page 136 of 146 rej03b0188-0104 4559 group machine instructions (index by types) (continued) mnemonic instruction code number of words number of cycles function d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecim al notation other operation nop 0000000000000 1 1(pc) (pc) + 1 pof 0000000010002 1 1transition to clock operating mode pof2 0000001000008 1 1transition to ram back-up mode epof 000101101105b 1 1pof or pof2 instruction valid snzp 0000000011003 1 1(p) = 1 ? wrst 10101000002a0 1 1(wdf1) = 1 ? (wdf1) 0 dwdt 101001110029c 1 1stop of watc hdog timer function enabled srst 0000000001001 1 1system reset rupt 0001011000058 1 1(uptf) 0 supt 0001011001059 1 1(uptf) 1 svde 1010010011293 1 1at power down mode, voltage drop detection circuit valid snzvd 101000101028a 1 1(vdf) = 1? para meter type of instructi ons
rev.1.04 aug 23, 2007 page 137 of 146 rej03b0188-0104 4559 group skip condition carry flag cy detailed description ?? no operation; adds 1 to program counter value, and others remain unchanged. ?? puts the system in clock operating mode by executi ng the pof instruction after executing the epof instruction. ?? puts the system in ram back-up state by executi ng the pof2 instruction after executing the epof instruction. ?? makes the immediate after pof or pof2 instruct ion valid by executing the epof instruction. (p) = 1 ? skips the next instruction when the p flag is ?1?. after skipping, the p flag remains unchanged. executes the next instruct ion when the p flag is ?0?. (wdf1) = 1 clears (0) to the wdf1 flag and skips the next inst ruction when watchdog timer flag wdf1 is ?1?. when the wdf1 flag is ?0?, executes the nex t instruction. also, stops the watc hdog timer function when executing the wrst instruction immediately after the dwdt instruction. ?? stops the watchdog timer function by the wrst in struction after executi ng the dwdt instruction. ?? system reset occurs. ?? clears (0) to the high-order bit reference enable flag uptf. ?? sets (1) to the high-order bit reference enable flag uptf. (vdf) = 1 ? skips the next instruction when voltage drop detection ci rcuit flag vdf is ?1?. execute instruction when vpf is ?0?. after skipping, the cont ents of vdf remains unchanged. ?? validates the voltage drop detec tion circuit at power down (clock operating mode and ram back-up mode).
rev.1.04 aug 23, 2007 page 138 of 146 rej03b0188-0104 4559 group the above table shows the relations hip between machine language codes and machine language instructions. d 3? d 0 show the low-order 4 bits of the machine language code, and d 9? d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is al so provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked ??.? the codes for the second word of a two-word instruction are described below. instruction code table d 9 ? d 4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 00 1111 010000 to 010111 011000 to 011111 d 3 ? d 0 hex, notation 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 ? 17 18 ? f 0000 0 nop bla szb 0 bmla ? tasp a 0 la 0 tabp 0 tabp 16 tabp 32 ? bml bml bl bl bm b 0001 1 srst cld szb 1 ?? tad a 1 la 1 tabp 1 tabp 17 tabp 33 ? bml bml bl bl bm b 0010 2 pof ? szb 2 ?? tax a 2 la 2 tabp 2 tabp 18 tabp 34 ? bml bml bl bl bm b 0011 3 snzp iny szb 3 ?? taz a 3 la 3 tabp 3 tabp 19 tabp 35 ? bml bml bl bl bm b 0100 4 di rd szd ? rt tav1 a 4 la 4 tabp 4 tabp 20 tabp 36 ? bml bml bl bl bm b 0101 5 ei sd sean ? rts tav2 a 5 la 5 tabp 5 tabp 21 tabp 37 ? bml bml bl bl bm b 0110 6 rc ? seam ? rti ? a 6 la 6 tabp 6 tabp 22 tabp 38 ? bml bml bl bl bm b 0111 7 sc dey ???? a 7 la 7 tabp 7 tabp 23 tabp 39 ? bml bml bl bl bm b 1000 8 pof2 and ? snz0 lz 0 rupt a 8 la 8 tabp 8 tabp 24 tabp 40 ? bml bml bl bl bm b 1001 9 ? or tda ? lz 1 supt a 9 la 9 tabp 9 tabp 25 tabp 41 ? bml bml bl bl bm b 1010 a am teab tabe snzi 0 lz 2 ? a 10 la 10 tabp 10 tabp 26 tabp 42 ? bml bml bl bl bm b 1011 b amc ??? lz 3 epof a 11 la 11 tabp 11 tabp 27 tabp 43 ? bml bml bl bl bm b 1100 c tya cma ?? rb 0 sb 0 a 12 la 12 tabp 12 tabp 28 tabp 44 ? bml bml bl bl bm b 1101 d ? rar ?? rb 1 sb 1 a 13 la 13 tabp 13 tabp 29 tabp 45 ? bml bml bl bl bm b 1110 e tba tab ? tv2a rb 2 sb 2 a 14 la 14 tabp 14 tabp 30 tabp 46 ? bml bml bl bl bm b 1111 f ? tay szc tv1a rb 3 sb 3 a 15 la 15 tabp 15 tabp 31 tabp 47 ? bml bml bl bl bm b the second word bl 10 paaa aaaa bml 10 paaa aaaa bla 10 pp00 pppp bmla 10 pp00 pppp sea 00 0111 nnnn szd 00 0010 1011
rev.1.04 aug 23, 2007 page 139 of 146 rej03b0188-0104 4559 group the above table shows the relations hip between machine language codes and machine language instructions. d 3? d 0 show the low-order 4 bits of the machine language code, and d 9? d 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is al so provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked ??.? the codes for the second word of a two-word instruction are described below. instruction code table d 9 ? d 4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 10 1111 110000 to 111111 d 3 ? d 0 hex, notation 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 ? 3f 0000 0 ? tw3a op0a t1ab ?? iap0 tab1 snzt 1 ? wrst tma 0 tam 0 xam 0 xami 0 xamd 0 lxy 0001 1 ? tw4a op1a t2ab ?? iap1 tab2 snzt 2 ?? tma 1 tam 1 xam 1 xami 1 xamd 1 lxy 0010 2 ?? op2a ?? tamr iap2 ? snzt 3 ?? tma 2 tam 2 xam 2 xami 2 xamd 2 lxy 0011 3 ?? op3a ?? tai1 iap3 ?? svde ? tma 3 tam 3 xam 3 xami 3 xamd 3 lxy 0100 4 ? tk1a ??????? t2ha b ? tma 4 tam 4 xam 4 xami 4 xamd 4 lxy 0101 5 ? tk2a ? tpsab ??? tabps ? t2r2 l ? tma 5 tam 5 xam 5 xami 5 xamd 5 lxy 0110 6 ? tmra tc3a ?? tak0 ????? tma 6 tam 6 xam 6 xami 6 xamd 6 lxy 0111 7 ? ti1a ??? tapu0 ????? tma 7 tam 7 xam 7 xami 7 xamd 7 lxy 1000 8 tpu3a ? tfr0a ??????? tc1a tma 8 tam 8 xam 8 xami 8 xamd 8 lxy 1001 9 trga ? tfr1a ?? tak1 ???? tc2a tma 9 tam 9 xam 9 xami 9 xamd 9 lxy 1010 a tl1a ? tfr2a ? tal1 tak2 ?? snzv d ? tpaa tma 10 tam 10 xam 10 xami 10 xamd 10 lxy 1011 b tl2a tk0a tfr3a ? taw1 tak3 ??? crck ? tma 11 tam 11 xam 11 xami 11 xamd 11 lxy 1100 c tl3a ? tk3a ? taw2 ??? rcp dwdt ? tma 12 tam 12 xam 12 xami 12 xamd 12 lxy 1101 d tlca ? tpu0a ? taw3 tapu3 ?? scp ?? tma 13 tam 13 xam 13 xami 13 xamd 13 lxy 1110 e tw1a ? tpu1a ? taw4 tapu1 ????? tma 14 tam 14 xam 14 xami 14 xamd 14 lxy 1111 f tw2a ? tpu2a tr1ab ? tapu2 ????? tma 15 tam 15 xam 15 xami 15 xamd 15 lxy the second word bl 10 paaa aaaa bml 10 paaa aaaa bla 10 pp00 pppp bmla 10 pp00 pppp sea 00 0111 nnnn szd 00 0010 1011
rev.1.04 aug 23, 2007 page 140 of 146 rej03b0188-0104 4559 group electrical characteristics absolute maximum ratings table 30 absolute maximum ratings symbol parameter conditions ratings unit v dd supply voltage - ? 0.3 to 6.5 v v i input voltage p0, p1, p2, p3, d 0 -d 5 , reset , x in , x cin , int, cntr - ? 0.3 to v dd +0.3 v v o output voltage p0, p1, p2, p3, d 0 ? d 7 , reset output transistors in cut-off state ? 0.3 to v dd +0.3 v v o output voltage c/cntr, x out , x cout - ? 0.3 to v dd +0.3 v v o output voltage seg 0 to seg 31 , com 0 to com 3 - ? 0.3 to v dd +0.3 v p d power dissipation ta = 25 c300mw t opr operating temperature range - ? 20 to 85 c t stg storage temperature range - ? 40 to 125 c
rev.1.04 aug 23, 2007 page 141 of 146 rej03b0188-0104 4559 group recommended operating conditions note 1. at 1/2 bias: v lc1 = v lc2 = (1/2)?v lc3 at 1/3 bias: v lc1 = (1/3)?v lc3 , v lc2 = (2/3)?v lc3 note 2. the average output current is the average value during 100ms. table 31 recommended operating conditions 1 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v dd supply voltage (with a ceramic resonator) f(stck) 6mhz 4 5.5 v f(stck) 4.4mhz 2.7 5.5 f(stck) 2.2mhz 2 5.5 f(stck) 1.1mhz 1.8 5.5 v dd supply voltage (when an external clock is used) f(stck) 4.8mhz 4 5.5 v f(stck) 3.2mhz 2.7 5.5 f(stck) 1.6mhz 2 5.5 f(stck) 0.8mhz 1.8 5.5 v dd supply voltage (when rc oscillation is used) f(stck) 4.4 mhz 2.7 5.5 v v dd supply voltage (when quartz-crystal oscillation is used) f(stck) 50 khz 1.8 5.5 v v dd supply voltage (when on-chip oscillation is used) 1.8 5.5 v v ram ram back-up voltage (at ram back-up) 1.6 5.5 v v ss supply voltage 0v v lc3 lcd power supply (note 1) 1.8 v dd v v ih ?h? level input voltage p0, p1, p2, p3, d 0 ? d 5 0.8v dd v dd v x in , x cin 0.7v dd v dd reset 0.85v dd v dd int 0.85v dd v dd cntr 0.8v dd v dd v il ?l? level input voltage p0, p1, p2, p3, d 0 ? d 5 00.2v dd v x in , x cin 00.3v dd reset 00.3v dd int 00.15v dd cntr 0 0.15v dd i oh(peak) ?h? level peak output current p0, p1, p2, p3, d 0 ? d 5 v dd = 5v ? 20 ma v dd = 3v ? 10 c/cntr v dd = 5v ? 30 v dd = 3v ? 15 i oh(avg) ?h? level average output current (note 2) p0, p1, p2, p3, d 0 ? d 5 v dd = 5v ? 10 ma v dd = 3v ? 5 c/cntr v dd = 5v ? 20 v dd = 3v ? 10 i ol(peak) ?l? level peak output current p0, p1, p2, p3, d 0 ? d 7 , c/cntr v dd = 5v 24 ma v dd = 3v 12 reset v dd = 5v 10 v dd = 3v 4 i ol(avg) ?l? level average output current (note 2) p0, p1, p2, p3, d 0 ? d 7 , c/cntr v dd = 5v 15 ma v dd = 3v 7 reset v dd = 5v 5 v dd = 3v 2 i oh(avg) ?h? level total average current p0, c/cntr ? 40 ma p1, p2, p3, d 0 ? d 5 ? 40 i ol(avg) ?l? level total average current p0, c/cntr 40 ma p1, p2, p3, d 0 ? d 7 , reset 40
rev.1.04 aug 23, 2007 page 142 of 146 rej03b0188-0104 4559 group note 1. the frequency is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the frequency limits. note 2. if the rising time exceeds the maximum rati ng value, connect a capacitor between the reset pin and vss at the shortest distance, and input ?l? level to reset pin until the value of supply volta ge reaches the minimum operating voltage. fig 82. system clock (stck) operating condition map table 32 recommended operating conditions 2 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. f(x in ) oscillation frequency (with a ceramic resonator) f(stck) = f(x in )v dd = 4.0 v to 5.5 v 6 mhz v dd = 2.7 v to 5.5 v 4.4 v dd = 2 v to 5.5 v 2.2 v dd = 1.8 v to 5.5 v 1.1 f(stck) = f(x in )/2 v dd = 2.7 v to 5.5 v 6 v dd = 2 v to 5.5 v 4.4 v dd = 1.8 v to 5.5 v 2.2 f(stck) = f(x in )/4, f(x in )/8 v dd = 2 v to 5.5 v 6 v dd = 1.8 v to 5.5 v 4.4 f(x in ) oscillation frequency (with an external clock input) f(stck) = f(x in )v dd = 4 v to 5.5 v 4.8 mhz v dd = 2.7 v to 5.5 v 3.2 v dd = 2 v to 5.5 v 1.6 v dd = 1.8 v to 5.5 v 0.8 f(stck) = f(x in )/2 v dd = 2.7 v to 5.5 v 4.8 v dd = 2 v to 5.5 v 3.2 v dd = 1.8 v to 5.5 v 1.6 f(stck) = f(x in )/4, f(x in )/8 v dd = 2 v to 5.5 v 4.8 v dd = 1.8 v to 5.5 v 3.2 f(x in ) oscillation frequency (at rc oscillation) (note 1) v dd = 2.7 to 5.5 v 4.4 mhz f(x cin ) oscillation frequency (at quarts-crystal oscillation) quartz-crystal oscillator 50 khz f(cntr) timer external input frequency cntr f(stck)/6 hz tw(cntr) timer external input period (?h? and ?l? pulse width) cntr 3/f(stck) s t pon power-on reset circuit valid supply voltage rising time (note 2) v dd = 0 1.8v 100 s 1.1 2.2 4.4 6 1.8 2 2.7 4 5.5 recommended operating conditions with a ceramic resonator f(stck) [mhz] v dd [v] 0.8 1.6 3.2 4.8 1.8 2 2.7 4 5.5 recommended operating conditions at external clock oscillation f(stck) [mhz] v dd [v] 4.4 2.7 5.5 recommended operating conditions at rc oscillation f(stck) [mhz] v dd [v] 50 1.8 5.5 recommended operating conditions at quartz-crystal oscillation f(stck) [khz] v dd [v]
rev.1.04 aug 23, 2007 page 143 of 146 rej03b0188-0104 4559 group electrical characteristics note 1. when rc oscillati on is used, use the external 33 pf capacitor (c). note 2. the impedance state is the resistor value of the output voltage. at v lc3 level output: v o = 0.8 v lc3 at v lc2 level output: v o = 0.8 v lc2 at v lc1 level output: v o = 0.2 v lc2 + v lc1 at v ss level output: v o = 0.2 v lc1 table 33 electrical charac teristics 1 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? level output voltage p0, p1, p2, p3, d 0 ? d 5 v dd = 5v i oh = ? 10ma 3 v i oh = ? 3ma 4.1 v dd = 3v i oh = ? 5ma 2.1 i oh = ? 1ma 2.4 v oh ?h? level output voltage c/cntr v dd = 5v i oh = ? 20ma 3 v i oh = ? 6ma 4.1 v dd = 3v i oh = ? 10ma 2.1 i oh = ? 3ma 2.4 v ol ?l? level output voltage p0, p1, p2, p3, d 0 ? d 7 c/cntr v dd = 5v i ol = 15ma 2 v i ol = 5ma 0.9 v dd = 3v i ol = 9ma 1.4 i ol = 3ma 0.9 v ol ?l? level output voltage reset v dd = 5v i ol = 5ma 2 v i ol = 1ma 0.6 v dd = 3v i ol = 2ma 0.9 i ih ?h? level input current p0, p1, p2, p3, d 0 ? d 5 reset , x in , x cin , int cntr v i = v dd 2 a i il ?l? level input current p0, p1, p2, p3, d 0 ? d 5 reset , x in , x cin , int cntr v i = 0v p0, p1, p2, p3 no pull-up ? 2 a r pu pull-up resistor value p0, p1, p2, p3 reset v i = 0v v dd = 5v 30 60 125 k ? v dd = 3v 50 120 250 v t+ ? v t ? hysteresis reset v dd = 5v 1 v v dd = 3v 0.4 v t+ ? v t ? hysteresis int v dd = 5v 0.6 v v dd = 3v 0.3 v t+ ? v t ? hysteresis cntr v dd = 5v 0.2 v v dd = 3v 0.2 f(ring) on-chip oscillator clock frequency v dd = 5v 200 500 700 khz v dd = 3v 100 250 400 ? f(x in ) frequency error (with rc oscillation, error of external rc not included) (note 1) v dd = 5v 10 %, ta = center 25 c 17 % v dd = 3v 10 %, ta = center 25 c 17 r com com output impedance (note 2) v dd = 5v 1.5 7.5 k ? v dd = 3v 2 10 r seg seg output impedance (note 2) v dd = 5v 1.5 7.5 k ? v dd = 3v 2 10 r vlc internal resistor for lcd power supply when dividing resistor 2r 3 selected 300 600 1200 k ? when dividing resistor 2r 2 selected 200 400 800 when dividing resistor r 3 selected 150 300 600 when dividing resistor r 2 selected 100 200 400
rev.1.04 aug 23, 2007 page 144 of 146 rej03b0188-0104 4559 group note 1. the voltage drop detection circuit operation current (i rst ) is added. note 2. when the internal dividing resistors for lcd power are used , the current values according to using resistor values are a dded. table 34 electrical charac teristics 2 (ta = ?20 c to 85 c, v dd = 1.8 to 5.5 v, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. i dd supply current at active mode (with a ceramic oscillator) (1, 2) v dd = 5v f(x in ) = 6mhz f(ring) = stop f(x cin ) = stop f(stck) = f(x in )/8 1.2 2.4 ma f(stck) = f(x in )/4 1.3 2.6 f(stck) = f(x in )/2 1.6 3.2 f(stck) = f(x in )2.24.4 v dd = 5v f(x in ) = 4mhz f(ring) = stop f(x cin ) = stop f(stck) = f(x in )/8 0.9 1.8 ma f(stck) = f(x in )/4 1 2 f(stck) = f(x in )/2 1.2 2.4 f(stck) = f(x in )1.63.2 v dd = 3v f(x in ) = 4mhz f(ring) = stop f(x cin ) = stop f(stck) = f(x in )/8 0.3 0.6 ma f(stck) = f(x in )/4 0.4 0.8 f(stck) = f(x in )/2 0.5 1 f(stck) = f(x in )0.71.4 at active mode (with a quartz-crystal oscillator) (1, 2) v dd = 5v f(x in ) = stop f(ring) = stop f(x cin ) = 32 khz f(stck) = f(x cin )/8 7 14 a f(stck) = f(x cin )/4 8 16 f(stck) = f(x cin )/2 10 20 f(stck) = f(x cin )1428 v dd = 3v f(x in ) = stop f(ring) = stop f(x cin ) = 32 khz f(stck) = f(x cin )/8 5 10 a f(stck) = f(x cin )/4 6 12 f(stck) = f(x cin )/2 7 14 f(stck) = f(x cin )816 at active mode (with an on-chip oscillator) (1, 2) v dd = 5v f(x in ) = stop f(ring) = active f(x cin ) = stop f(stck) = f(ring)/8 50 100 a f(stck) = f(ring)/4 60 120 f(stck) = f(ring)/2 80 160 f(stck) = f(ring) 120 240 v dd = 3v f(x in ) = stop f(ring) = active f(x cin ) = stop f(stck) = f(ring)/8 10 20 a f(stck) = f(ring)/4 13 26 f(stck) = f(ring)/2 19 38 f(stck) = f(ring) 31 62 at clock operation mode (pof instruction execution) (1, 2) f(x cin ) = 32 khz v dd = 5v 6 12 a v dd = 3v 5 10 at ram back-up mode (pof2 instruction execution) (1) ta = 2 5 c0.13 a v dd = 5v 10 v dd = 3v 6
rev.1.04 aug 23, 2007 page 145 of 146 rej03b0188-0104 4559 group voltage drop detection circuit characteristics note 1. the detection voltage (v rst ? ) is defined as the voltage when reset occurs when the supply voltage (v dd ) is falling. note 2. the detection voltage (v rst +) is defined as the voltage when re set is released when the supply voltage (v dd ) is rising from reset occurs. note 3. when the supply voltage goes lower than the detection voltage (v skip ), the voltage drop detection circuit interrupt request flag (vdf) is set to ?1?. note 4. voltage drop detection circuit operation current (i rst ) is added to i dd (power current) when voltage dr op detection ci rcuit is used. note 5. the detection time (t rst ) is defined as the time until rese t occurs when the supply voltage (v dd ) is falling to [v rst - ? 0.1v]. basic timing diagram table 35 voltage drop detection circuit characteristics (ta = ?20 c to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v rst - detection voltage (reset occurs) (note 1) ta = 2 5 c1.7v ? 20 c ta < 0 c1.62.2 0 c ta < 50 c1.32.1 50 c ta 85 c1.11.8 v rst+ detection voltage (reset release) (note 2) ta = 2 5 c1.8v ? 20 c ta < 0 c1.72.3 0 c ta < 50 c1.42.2 50 c ta 85 c1.21.9 v skip detection voltage (skip occurs) (note 3) ta = 2 5 c2v ? 20 c ta < 0 c1.92.5 0 c ta < 50 c1.62.4 50 c ta 85 c1.42.1 v rst + ? v rst - detection voltage hysteresis 0.1 v i rst operation current (note 4) v dd = 5v 30 60 a v dd = 3v 15 30 v dd = 1.8v 6 12 t rst detection time (note 5) v dd (v rst - ? 0.1v) 0.2 1.2 ms system clock stck port output d 0 to d 7 p0 0 to p0 3 p1 0 to p1 3 p2 0 to p2 3 p3 0 to p3 3 , c port input d 0 to d 5 p0 0 to p0 3 p1 0 to p1 3 p2 0 to p2 3 p3 0 to p3 3 interrupt input int parameter pin name machine cycle mi mi + 1
rev.1.04 aug 23, 2007 page 146 of 146 rej03b0188-0104 4559 group package outline include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x y * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e under development
(1/1) revision history 4559 group datasheet rev. date description page summary 1.00 jul 27, 2006 - first edition issued 1.01 apr 27, 2007 58 fig56 stabilizing time b, d: (system clock division ratio 15 ) times. (system clock division ratio 171 ) times. 1.02 may 25, 2007 all pages ?preliminary? deleted 1.03 may 30, 2007 32 fig33 orclk orclk 33 fig34 w3 0 w3 3 34,74 w3 3 timer 3 count source selection bit 1 : prescaler output (orclk)/2 prescaler output (orclk) 1.04 aug 23, 2007 4 timer 1, timer 2 explanation of function revised. segment output ?28? ?32? 21 fig. 21 13ff 16 17ff 16 25 (7)interrupt sequence revised. 34 pa0 0 ?stop (state initialized)? ?stop (state retained)? w30, w31 ?timer 3 count source selection bits? ?timer 3 count value selection bits? w3 0 0 ?x in input? ?x cin input? 55 table 23: note 4 is revised. 57 fig. 56 note 7 added. 65, 66, 67 qzrom writing mode added. 69 (2) bit 3 of register i1 ?(register l10=?0?)? ?(register k20=?0?)? (3) bit 2 of register i1 ?the exter nal 1 interrupt request flag (exf0)? ?the external 0 interrupt request flag (exf0)? 71 (27) data required for qzrom writing orders added. 72 fig. 76 note added. 73 fig. 77 ?v cc ? ?v dd ? 77 pa 0 prascaler control bit 0 ?stop (state initialized)? ?stop (state retained)? w3 0 , w3 1 ?timer 3 count source selection bits? ?timer 3 count value selection bits? 84, 85, 86 index pages added. 109 taw4 operation: ?(a) (w5)? ?(a) (w4)? 1/2 all trademarks and registered trademarks are the property of their respective owners. revision history
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